JPS5940537A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5940537A JPS5940537A JP57149401A JP14940182A JPS5940537A JP S5940537 A JPS5940537 A JP S5940537A JP 57149401 A JP57149401 A JP 57149401A JP 14940182 A JP14940182 A JP 14940182A JP S5940537 A JPS5940537 A JP S5940537A
- Authority
- JP
- Japan
- Prior art keywords
- fixed
- gold alloy
- semiconductor element
- wedge
- solder material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 10
- 238000005219 brazing Methods 0.000 claims 1
- 229910001020 Au alloy Inorganic materials 0.000 abstract description 18
- 239000003353 gold alloy Substances 0.000 abstract description 18
- 238000003825 pressing Methods 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract 4
- 229910015365 Au—Si Inorganic materials 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000005496 eutectics Effects 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 10
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000587161 Gomphocarpus Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 244000144992 flock Species 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
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- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
- H01L2224/78314—Shape
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- H01L2224/78318—Shape of other portions inside the capillary
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
従来、半導体素子を金属基板上に定着する方法として、
いわゆる−ネイルヘッドボンデ、イングにより金属基板
上に一端が接着されて立設している短い金合金線を、下
面の平らなハンマで押しつぶして形成した全薄層の上に
シリコンよりなる半導体素子を圧接し、前記半導体素子
の装面に金−シリコン共晶合金層を形成せしめることに
より半導体素子を金属基板上に定着させる方法が提案実
施されている。そして、半導体素子を定着するのに適し
た長さに金合金線を切断するにあたって、水素トーチで
行うのは種々の不都合を生ずるため通常、電気トーチが
用いられる。Conventionally, as a method for fixing semiconductor elements on metal substrates,
A semiconductor element made of silicon is placed on a thin layer formed by crushing a short gold alloy wire, one end of which is bonded to a metal substrate and erected using so-called nail head bonding, using a hammer with a flat bottom surface. A method has been proposed and implemented in which a semiconductor element is fixed on a metal substrate by press-welding and forming a gold-silicon eutectic alloy layer on the surface of the semiconductor element. When cutting the gold alloy wire to a length suitable for fixing a semiconductor element, an electric torch is usually used since using a hydrogen torch causes various inconveniences.
しかしながら、電気トーチによる切断(J、金合金線の
先端に形成される金ボールの径にバラツキを生じ易く、
ひいては金合金線の貫通されているキャピラリのツマリ
等を招来し生産能率を低トさせる。However, cutting with an electric torch (J) tends to cause variations in the diameter of the gold ball formed at the tip of the gold alloy wire.
As a result, the capillary through which the gold alloy wire is passed may become jammed, reducing production efficiency.
また、立設した金合金線をハンマて押l、っぷず場合、
その押さえ方によって金合金線の倒れる方向が異るため
、全薄層の形成される位置にバラツキを生じる。そのた
め、通常、自動機でもって金属基板−りの一定の位置に
置かれる半導体素子と前記全薄層との融着面積にバラツ
キを生する結果、半導体素子の電気的特性が不安定にな
るという欠点がある。In addition, if you press the vertical gold alloy wire with a hammer,
The direction in which the gold alloy wire falls varies depending on how it is pressed, resulting in variations in the positions where all the thin layers are formed. As a result, the electrical characteristics of the semiconductor element become unstable as a result of variations in the area of fusion between the semiconductor element and the entire thin layer, which are usually placed at a certain position on a metal substrate using an automatic machine. There are drawbacks.
さらに、電気トーチによる切断をもってしても、金合金
線の長さは最低1rrm程度までであるため、それ以下
の小さい寸法の半導体素子を定j−1−るために必要な
金合金の量としては過多になり、無駄を生ずるという欠
点がある。Furthermore, even when cut with an electric torch, the length of the gold alloy wire is at least about 1 rrm, so the amount of gold alloy required to define a semiconductor element with smaller dimensions than that is The disadvantage is that there are too many of them, resulting in waste.
本発明は上記事情に鑑みてなされたもので、半導体素子
を定着する装置のトラブルを少くして生産能率を向」二
できる半導体装置の生産方法を提供することを目的とし
ている。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for producing a semiconductor device that can improve production efficiency by reducing troubles in an apparatus for fixing semiconductor elements.
また、本発明の他の目的は金属基板」二に合金線を位置
的にバラツキなく形成できる半導体装1uの生産方法を
提供することにある。Another object of the present invention is to provide a method for producing a semiconductor device 1u in which alloy wires can be formed on a metal substrate 2 without positional variation.
さらに、本発明は金合金線の長さを例えは、定着される
半導体素子の寸法に応じて充分短くできる半導体装置の
製造方法を提供することも目的としている。A further object of the present invention is to provide a method for manufacturing a semiconductor device in which the length of the gold alloy wire can be sufficiently shortened depending on the dimensions of the semiconductor element to be fixed.
そして、そのために本発明は半導体素子の定着される金
属基板の所定位置に、所要長さの線状のろう接材料の両
端をウェッジでもって加圧接着し、前記接着されたろう
接材料を介して半導体素子を金属基板に定着させること
を特徴としている。。To this end, the present invention uses a wedge to pressure bond both ends of a linear soldering material of a required length to a predetermined position of a metal substrate on which a semiconductor element is to be fixed, and to connect the soldering material through the bonded soldering material. It is characterized by fixing a semiconductor element to a metal substrate. .
以下、本発明に係る半導体装置の製造方法の実施例につ
いて説明する。Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below.
第1図は本発明に係る方法の一実施例を略本する斜視図
である1−4第1図において1は金属製のボンディング
ツールであり、このボンディングツール1の先端部は階
段状に切り欠かれて、先端にウェッジを形成するととも
に、前記切り欠か41/、−傾斜面に小孔2が開設され
ている。ぞ[7て、小孔2には線状のろう接材料として
の例えば、金合金線3がとおされている。4は半導体装
r−の定7#′X1される金属基板としての例えば、リ
ードフレーム・、5はシリコンよりなる半導体素子、6
は半導体素子5を吸着して、これに振動を与えつつリー
ドフレーム4に接着された金合金線3の上に加圧するこ
とにより半導体素子5をリードフレーム4の所定位置に
定着させる金属製のコレット、7はリードフレーム等を
加熱するヒーターブロックである。FIG. 1 is a perspective view schematically showing an embodiment of the method according to the present invention. 1-4 In FIG. 1, 1 is a metal bonding tool, and the tip of this bonding tool 1 is cut into a step shape. The cutout forms a wedge at the tip, and a small hole 2 is opened in the notch 41/- and the inclined surface. [7] A wire-like soldering material, such as a gold alloy wire 3, is passed through the small hole 2. 4 is a metal substrate, for example, a lead frame, on which the semiconductor device r- is fixed 7#'X1; 5 is a semiconductor element made of silicon; 6
is a metal collet that fixes the semiconductor element 5 at a predetermined position on the lead frame 4 by adsorbing the semiconductor element 5 and applying pressure to the gold alloy wire 3 bonded to the lead frame 4 while applying vibration. , 7 is a heater block that heats the lead frame and the like.
すなわち、第1図ビ)に示すようにホンディングツール
1を半解体素子の定着されるべきリードフレーム4の所
定位置の上方に移動せしめ、同図(ロ)〜に)に示すよ
うにボンディングツール1の先端のウェッジでもって加
圧すること等により所要長さの金合金線3の両端をリー
ドフレーム4上に接着する。このようにして、例えば定
着される半導体素子の寸法に応じて必要な本数の金合金
線3を接着する。かかる金合金線の接着位置は、ウェッ
ジを用いる方法によると、所望位置より50μIl1以
内に、また、その長さは0.3v+m程度までそオ]ぞ
11制御することができる。そして、リードフレーム4
を例えは、金−シリコンの共晶温度に関連して定められ
る温度に才で加熱し、同図(へ)及び(ト1に示すよう
に例えばコレット6に吸着した半導体素子5をリードフ
レーム41−2の金合金線に加圧して若干の振動を与え
ると、半導体素子5の裏面に金−シリコン共晶合金層が
形成さね、前記半解体素子5がリードフレーム4に定着
される。That is, as shown in FIG. 1 B), the bonding tool 1 is moved above the predetermined position of the lead frame 4 where the half-dismantled element is to be fixed, and the bonding tool 1 is moved as shown in FIG. Both ends of the gold alloy wire 3 of a required length are bonded onto the lead frame 4 by applying pressure with a wedge at the tip of the lead frame 4. In this way, a required number of gold alloy wires 3 are bonded, depending on the dimensions of the semiconductor element to be fixed, for example. According to the method using a wedge, the adhesion position of the gold alloy wire can be controlled to within 50μIl1 from the desired position, and its length can be controlled to about 0.3V+m. And lead frame 4
For example, as shown in FIGS. When the gold alloy wire No. -2 is pressurized and slightly vibrated, a gold-silicon eutectic alloy layer is formed on the back surface of the semiconductor element 5, and the half-disassembled element 5 is fixed to the lead frame 4.
以上の実施例の説明より明らかなように、本発明に係る
半導体装置の製造方法は、半導体素子の定着される金属
基板の所定位置に、所要長さの線状のろう接材料の両端
をウェッジでもって直接加圧接着し、前記接着されたろ
う接祠料を介して半導体素子を金属基板に定着させるも
のであるから、両端の接着された線状のろう接材料をた
とえ押しつぶしても著しい位置ズレを起こすことはない
。As is clear from the description of the embodiments above, the method for manufacturing a semiconductor device according to the present invention is to wedge both ends of a linear soldering material of a required length to a predetermined position of a metal substrate on which a semiconductor element is fixed. Since the semiconductor element is bonded directly under pressure and fixed to the metal substrate through the bonded soldering material, even if the linear soldering material bonded at both ends is crushed, there will be no significant positional shift. will not occur.
それ故、半導体素子と前記ろう接材料との融着面積のバ
ラツキが小さくなるので半解体素子の電気的特性を安定
させることができる。Therefore, variations in the fused area between the semiconductor element and the soldering material are reduced, so that the electrical characteristics of the half-disassembled element can be stabilized.
また、本発明はウェッジでろう接材料を直接加圧接着し
ているので、比較的装置のトラブルか少く生産能率を向
上できるとともに、ろう接材料の長さも充分短くするこ
とができるので材オニ′1費を低減することができる。Furthermore, since the present invention uses a wedge to bond the soldering material directly under pressure, production efficiency can be improved with relatively little equipment trouble, and the length of the soldering material can also be sufficiently shortened, so that the material can 1 cost can be reduced.
゛゛
【図面の簡単な説明】
第1図は本発明に係る方法の一実施例を略本する斜視図
である。
1・・・ボンディングツール、2・・・小孔、3・・・
金合金線、4・・・リードフレーム、訃・・半解体素子
、6・・・コレット、7・・・ヒーターフロック。
特許出願人 ローム株式会社
代理人弁理士大西孝治
第1図
(ホ)(−)
(ハ) (ニ)
171BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic perspective view of an embodiment of the method according to the invention. 1... Bonding tool, 2... Small hole, 3...
Gold alloy wire, 4... Lead frame, Semi-disassembled element, 6... Collet, 7... Heater flock. Patent Applicant: Koji Onishi, Patent Attorney, ROHM Co., Ltd. Figure 1 (E) (-) (C) (D)
171
Claims (1)
の両端を加圧接着し、前記接着されたろう接材料を介(
7て半導体素子を金属基板に定着させることを特徴とす
る半導体装置の製造方法。Both ends of a linear brazing material are bonded under pressure to the metal substrate on which the semiconductor element is fixed, and the (
7. A method for manufacturing a semiconductor device, comprising: fixing a semiconductor element on a metal substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57149401A JPS5940537A (en) | 1982-08-28 | 1982-08-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57149401A JPS5940537A (en) | 1982-08-28 | 1982-08-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5940537A true JPS5940537A (en) | 1984-03-06 |
Family
ID=15474318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57149401A Pending JPS5940537A (en) | 1982-08-28 | 1982-08-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5940537A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6266641A (en) * | 1985-09-19 | 1987-03-26 | Rohm Co Ltd | Die bonding method for semiconductor pellet |
JPS63232340A (en) * | 1987-11-13 | 1988-09-28 | Sanyo Electric Co Ltd | Device for applying foil |
JPH01270324A (en) * | 1988-04-22 | 1989-10-27 | Mitsubishi Electric Corp | Fixation of semiconductor chip |
CN103887183A (en) * | 2012-12-21 | 2014-06-25 | 华为技术有限公司 | Gold/silicon eutectic chip welding method and transistor |
CN104319242A (en) * | 2014-10-27 | 2015-01-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Thick film substrate welding-flux-free eutectic crystal mounting method |
DE102016124750B4 (en) | 2016-12-19 | 2019-03-07 | Schaeffler Technologies AG & Co. KG | Device for changing the effective length of a connecting rod during the operation of a reciprocating internal combustion engine |
US10763192B2 (en) | 2017-12-07 | 2020-09-01 | Stmicroelectronics S.R.L. | Method of manufacturing semiconductor devices and corresponding semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50160773A (en) * | 1974-06-18 | 1975-12-26 |
-
1982
- 1982-08-28 JP JP57149401A patent/JPS5940537A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50160773A (en) * | 1974-06-18 | 1975-12-26 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6266641A (en) * | 1985-09-19 | 1987-03-26 | Rohm Co Ltd | Die bonding method for semiconductor pellet |
JPS63232340A (en) * | 1987-11-13 | 1988-09-28 | Sanyo Electric Co Ltd | Device for applying foil |
JPH01270324A (en) * | 1988-04-22 | 1989-10-27 | Mitsubishi Electric Corp | Fixation of semiconductor chip |
CN103887183A (en) * | 2012-12-21 | 2014-06-25 | 华为技术有限公司 | Gold/silicon eutectic chip welding method and transistor |
EP2768015A4 (en) * | 2012-12-21 | 2015-07-29 | Huawei Tech Co Ltd | Gold/silicon eutectic chip soldering method and transistor |
CN104319242A (en) * | 2014-10-27 | 2015-01-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Thick film substrate welding-flux-free eutectic crystal mounting method |
DE102016124750B4 (en) | 2016-12-19 | 2019-03-07 | Schaeffler Technologies AG & Co. KG | Device for changing the effective length of a connecting rod during the operation of a reciprocating internal combustion engine |
US10763192B2 (en) | 2017-12-07 | 2020-09-01 | Stmicroelectronics S.R.L. | Method of manufacturing semiconductor devices and corresponding semiconductor device |
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