JPH03116735A - Ic for flip chip and formation of bump thereof - Google Patents
Ic for flip chip and formation of bump thereofInfo
- Publication number
- JPH03116735A JPH03116735A JP1251769A JP25176989A JPH03116735A JP H03116735 A JPH03116735 A JP H03116735A JP 1251769 A JP1251769 A JP 1251769A JP 25176989 A JP25176989 A JP 25176989A JP H03116735 A JPH03116735 A JP H03116735A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wedge
- bump
- bumps
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 28
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000002788 crimping Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 239000011241 protective layer Substances 0.000 abstract description 2
- 229910001111 Fine metal Inorganic materials 0.000 abstract 1
- 239000011805 ball Substances 0.000 description 8
- 230000002950 deficient Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000011806 microball Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 241000587161 Gomphocarpus Species 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14143—Circular array, i.e. array with radial symmetry with a staggered arrangement, e.g. depopulated array
- H01L2224/14145—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＩＣの電極部上にバンプを形成しであるフリ
ップチップ用ＩＣおよび前記バンプの形成方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-chip IC in which bumps are formed on electrode portions of the IC, and a method for forming the bumps.
［従来技術］
フリップチップ用ＩＣとは、ペアチップＩＣの電極部に
金属や半田等でバジ′プを形成したものである。[Prior Art] A flip-chip IC is a pair-chip IC in which a bump is formed on the electrode portion of the IC using metal, solder, or the like.
一般にパッケージに収納されていないペアチップＩＣ（
集積回路）を基板に実装する方法としては、ワイヤーボ
ンデング法と、フリップチップボンデング法がある。Paired chip ICs that are generally not housed in a package (
There are two methods for mounting an integrated circuit (integrated circuit) on a substrate: a wire bonding method and a flip chip bonding method.
このフリップチップボンデング法に使用するＩＣをフリ
ップチップ用ＩＣと称している。The IC used in this flip chip bonding method is called a flip chip IC.
前記ワイヤーボンデング法は、特公昭６３−９４８＋に
開示されているように、ボールボンデング法（ネイルヘ
ッドボンデング法）とウェッジボンデング法に分類され
る。The wire bonding method is classified into a ball bonding method (nail head bonding method) and a wedge bonding method, as disclosed in Japanese Patent Publication No. 63-948+.
前記ポールボンデング法は、ボールボンダにより金属細
線の先端を加熱溶融してボール部を形成し、その加熱さ
れたボール部をボンデングキャピラリーによりベアーチ
ップＩＣの電極上に圧接変形させて接合することにより
、第１次ボンデングが完了する。ついで、ボンデングキ
ャピラリーを上昇させ、基板上の電極部と対面させて、
金属細線を同様に接合して第２次ボンデングをした後金
属細線はカットされる。The pole bonding method involves heating and melting the tip of a thin metal wire using a ball bonder to form a ball portion, and then pressing and deforming the heated ball portion onto the electrode of a bare chip IC using a bonding capillary to bond the wire. This completes the first bonding. Next, raise the bonding capillary so that it faces the electrode part on the substrate,
After the thin metal wires are similarly bonded and subjected to secondary bonding, the thin metal wires are cut.
前記ボンデングキャピラリーは、サファイア、ルビー、
セラミック等の耐熱材料で針状に形成され、上端から、
針状先端にかけて透孔が穿設され、透孔先端はアールが
形成されてロート状に孔が広がっている。前記透孔には
金属細線が挿入されている。そして、前記針状先端部で
溶融した金属細線を電極上に押圧して接合すると電極上
の金属細線端末形状は、上から見るとほぼ円形で、横か
ら見るとロート形状の突起が中央部にできることになる
。The bonding capillary is made of sapphire, ruby,
It is formed into a needle shape from heat-resistant material such as ceramic, and from the top end,
A through hole is drilled toward the needle-like tip, and the tip of the through hole is rounded and spreads out in a funnel shape. A thin metal wire is inserted into the through hole. When the molten metal wire is pressed onto the electrode by the needle-like tip and joined, the end shape of the metal wire on the electrode is approximately circular when viewed from above, and a funnel-shaped protrusion is formed in the center when viewed from the side. It will be possible.
又、前記ウェッジボンデング法は、ウェッジボンダによ
り金属細線の先端を超音波によりベアーチップＩＣの電
極上に超音波ボンデングする。In the wedge bonding method, the tip of a thin metal wire is ultrasonically bonded onto an electrode of a bare chip IC using an ultrasonic wave using a wedge bonder.
ウェッジボンダにはウェッジが配設され、このウェッジ
により金属細線の端末を電極上に圧接するのである。The wedge bonder is equipped with a wedge, which presses the end of the thin metal wire onto the electrode.
ウェッジの形状は、第１図に示すように側面には、金属
細線の入る孔が斜め下方向に設けられ、底面は平坦面で
ある。したがって、ウェッジボンダで接合された、金属
細線・の端末形状は、表面が平坦で一定の高さの圧接形
状となる。As shown in FIG. 1, the shape of the wedge is such that a hole into which a thin metal wire is inserted is provided diagonally downward on the side surface, and the bottom surface is flat. Therefore, the end shape of the thin metal wire bonded with the wedge bonder has a pressure-welded shape with a flat surface and a constant height.
次に、フリップチップボンデング法は、特開昭６２−２
９３７２９号に開示されているように、ペアチップＩＣ
の電極上に半田又は金属でバンプを形成し、基板上の電
極パターン上に、バンプを接触させ熱でバンプを溶かし
て接合するという金属細線を使用しない接合方法である
。Next, the flip chip bonding method was developed in Japanese Patent Application Laid-open No. 62-2
As disclosed in No. 93729, paired chip IC
This is a bonding method that does not use thin metal wires, in which bumps are formed with solder or metal on the electrodes of the substrate, the bumps are brought into contact with the electrode pattern on the substrate, and the bumps are melted and bonded with heat.
前記半田又は金属からなるバンプの形成方法の一例とし
て特開昭６３−２５５９２８号で開示されている。この
方法は、前述のワイヤーボンデング法に使用するボール
ボンダを利用して、ベアーチップＩＣの電極上に配設し
たキャピラリーから金属細線を繰り出し、金属細線の先
端に加熱により微小ボールを作る工程と、前記キャピラ
リーと金属細線とを下降させて前記微小ボールと上記電
極部、及びキャピラリーと微小ボールとを各々接触させ
、微小ボールと電極部を接合する工程と、前記キャピラ
リーを上昇させ、前記金属細線を引き上げて、金属細線
と前記微小ボールを切断する工程とにより電極上に金属
バンブを形成することができる。この方法で形成したバ
ンプは、ボールボンデング法で説明したようにキャピラ
リーを使用するのでバンプの中央に凸状部が形成されて
しまい、バンプの高さは６０〜１１００ｐと高くなって
しまう。このようなバンプは半田付けで接合する場合に
は、大きな熱量が必要となり、この半田付けの熱により
ベアーチップＩＣに不良ができるという問題点があった
。そこで特開昭６３−１５１０３１号や、日経マイクロ
デバイス、１９８７年９月号Ｐ１０７〜Ｐ１１５に開示
されているマイクロバンプボンデング法が開発された。An example of a method for forming bumps made of solder or metal is disclosed in Japanese Patent Laid-Open No. 63-255928. This method involves the process of drawing out a thin metal wire from a capillary placed on the electrode of a bare chip IC using the ball bonder used in the wire bonding method described above, and creating a minute ball at the tip of the thin metal wire by heating. , a step of lowering the capillary and the thin metal wire to bring the microball and the electrode portion into contact with each other, and a step of joining the microball and the electrode portion by bringing the capillary and the microball into contact with each other; and raising the capillary and bringing the thin metal wire into contact with each other. A metal bump can be formed on the electrode by pulling up the metal wire and cutting the fine ball. Since the bump formed by this method uses a capillary as explained in the ball bonding method, a convex portion is formed in the center of the bump, and the height of the bump is as high as 60 to 1100 p. When such bumps are joined by soldering, a large amount of heat is required, and there is a problem in that the soldering heat causes defects in the bare chip IC. Therefore, the microbump bonding method disclosed in Japanese Patent Application Laid-open No. 151031/1983 and Nikkei Microdevice, September 1987 issue, pages 107 to 115, was developed.
この方法に使用するフリップチップのバンプの高さはバ
ラ付きが少ないことが必要であることは周知であるが、
その他に本発明者等はバンプの高さが１０ｐｍ以下とそ
れ以上の場合に於いて、熱衝撃試験において不良率が大
いに変わることを発見した。第３図に、加熱サイクルと
不良率との相間々係をバンプの高さが１０１１ｍ以下の
場合と２０ｐｍの場合のデータを示す。このグラフから
もわかるようにバンプの高さが２０ｐｍの場合は１０ｐ
ｍ以下の場合に比較して不良率が非常に大きくなる。It is well known that the bump height of the flip chip used in this method needs to have little variation;
In addition, the present inventors have discovered that the failure rate in thermal shock tests varies greatly when the bump height is less than or equal to 10 pm and when it is greater than 10 pm. FIG. 3 shows the relationship between the heating cycle and the defective rate when the bump height is 1011 m or less and when the bump height is 20 pm. As you can see from this graph, if the bump height is 20pm, it is 10p.
The defective rate becomes extremely large compared to the case where the number is less than m.
［発明が解決しようとする問題点］
従来１０１１ｍ以下のバンプを作るには、メツキ法等で
作っていたが、ＩＣの種類によって電極の数も異なるの
でバンプの形成する位置が変わってくる。その度ごとに
マスクを作らなければならず、製造日数が多くなるとと
もにコストアップにもなるという問題点を有していた。[Problems to be Solved by the Invention] Conventionally, bumps of 1011 m or less have been made using a plating method, etc., but since the number of electrodes differs depending on the type of IC, the position where the bumps are formed changes. A mask has to be made each time, which increases the number of manufacturing days and increases costs.
そこで、本発明は、ワイヤーボンダでバンプを形成する
方法に着目しその方法をさらに改良して、バンプの高さ
が１０μｍ以下の一方向に長い形状のバンプをＩＣチッ
プの中心に向かって放射状に配列して接着強度の強いＩ
Ｃ及びＩＣのバンプを形成する方法を提供するものであ
る。Therefore, the present invention focuses on the method of forming bumps using a wire bonder and further improves the method to form bumps with a height of 10 μm or less in one direction and radially toward the center of the IC chip. Arranged with strong adhesive strength I
The present invention provides a method for forming C and IC bumps.
［問題点を解決するための手段Ｊ
本発明は、前述の問題点を解決するためになされたもの
で、ＩＣチップの電極部上に金属細線を圧着して細長い
形状で上面が平坦面を有し、高さが１０μｍ以下のバン
プをＩＣチップの中心に向かって放射状に配列させたこ
とを特徴とする。[Means for Solving the Problems J] The present invention has been made to solve the above-mentioned problems, and consists of a thin metal wire that is crimped onto the electrode portion of an IC chip to form an elongated shape with a flat upper surface. The IC chip is characterized in that bumps having a height of 10 μm or less are arranged radially toward the center of the IC chip.
さらに、本発明は、ＩＣチップの電極部上にウェッジボ
ンダにより金属細線を圧着して接合する工程と、前記接
合した金属細線の端部をカットする工程からなるフリッ
プチップ用ＩＣのバンブ形成方法であることをｒｆ徴と
する。Furthermore, the present invention provides a bump forming method for a flip chip IC, which comprises a step of crimping and bonding a thin metal wire onto the electrode portion of an IC chip using a wedge bonder, and a step of cutting the end of the bonded thin metal wire. A certain thing is called an RF sign.
［作用］
本発明のフリップチップ用ＩＣは、ＩＣチップの中心に
向かって放射状に細長い形状のバンプを形成させたので
熱により膨張収縮する方向と一致した方向にバンプが位
置するので、ＩＣチップを樹脂で固定する場合に樹脂の
応力を逃がすように作用する。[Function] The flip-chip IC of the present invention has elongated bumps radially formed toward the center of the IC chip, so the bumps are positioned in the same direction as the direction of expansion and contraction due to heat. When fixing with resin, it acts to relieve the stress of the resin.
［実施例］
ベアーチップＩＣを第１図で示すような、ウェッジボン
ダ１のステージ上にベアーチップＩＣ２を真空吸着で固
定する。前記ステージは１２０°Ｃ位に加熱されている
。次にＡｕ細線３を配設したウェッジ４を電極部となる
Ａ１パッド５上に載置し、超音波ホーン６により３０〜
６０ＫＨｚの超音波を加え、Ａｕ細線をＩＣチップ２の
Ａ１パッ＋：５上に圧着させる。[Example] A bare chip IC 2 is fixed by vacuum suction on the stage of a wedge bonder 1 as shown in FIG. The stage is heated to about 120°C. Next, the wedge 4 on which the Au thin wire 3 is arranged is placed on the A1 pad 5 that will become the electrode part, and the ultrasonic horn 6 is used to
Applying ultrasonic waves of 60 KHz, the Au thin wire is crimped onto the A1 pad +:5 of the IC chip 2.
ウェッジ４の底面は平坦面に形成されているのでＡｕ細
線は平らに潰されることになる。Since the bottom surface of the wedge 4 is formed as a flat surface, the Au thin wire is flattened.
ウェッジ４が上昇した後直上ないし直上付近に２回目の
ボンデングを行い、このときにクランプ８によりＡｕ細
線がクランプされて、引張られて、圧着端部から切断す
る。その後ウェッジ４が上昇してパッド上にバンプ７が
形成される。以上は２回のボンデングでバンプを形成す
る方法であるが、１回のボンデングのみで形成しても良
い。After the wedge 4 has been raised, second bonding is performed immediately above or near immediately above it, and at this time the Au thin wire is clamped and pulled by the clamp 8 and cut from the crimped end. Thereafter, the wedge 4 is raised to form a bump 7 on the pad. Although the above is a method of forming bumps by bonding twice, it is also possible to form bumps by bonding only once.
バンプ７の形状は、細長い形状で接着面積が大きくとれ
るように形成されている。実施例としては第２図に示す
ように長方形をしているが、長方形の他に楕円形や長三
角形や長台形でもよい。そしてバンプ７の向きは、中心
に向かって放射状に配列されている。このように放射状
に配列させることにより、プラスチックを使用してＩＣ
チップ上に保護層を設け、ＩＣチップを保護固定した場
合に前記プラスチックの応力を逃がすことができ接着の
信頼性が高くなる。The bump 7 has an elongated shape and is formed to have a large bonding area. In the embodiment, the shape is rectangular as shown in FIG. 2, but in addition to the rectangle, the shape may be an ellipse, an elongated triangle, or an elongated trapezoid. The bumps 7 are arranged radially toward the center. By arranging the IC radially in this way, plastic can be used to
When a protective layer is provided on the chip to protect and fix the IC chip, the stress of the plastic can be released and the reliability of adhesion is increased.
バンプの高さは、ウェッジ４の押圧力や超音波の出力を
変えることにより１０ｐｍ以下に形成する。本実施例で
はバンプの高さを８μｍとした。The height of the bump is formed to be 10 pm or less by changing the pressing force of the wedge 4 and the output of the ultrasonic wave. In this example, the height of the bump was 8 μm.
又、バンプの向きは、ステージを回転させることで放射
状に形成させることが可能となる。Furthermore, the bumps can be oriented radially by rotating the stage.
［効果］
以上説明したように、ウェッジボンダを使用して、ＩＣ
チップの電極上に上面が平坦面をしており、高さが１０
ＸＸｍ以下のバンプを形成させたので次のような効果を
有する。[Effect] As explained above, using a wedge bonder, IC
The top surface is flat on the electrode of the chip, and the height is 10
Since a bump of XXm or less is formed, the following effects are obtained.
（１） ウェッジボンダによりＩＣチップの電極上に
バンプが形成できる為に、作業工程が簡単で、安価にバ
ンプが形成できる効果を有している。(1) Since bumps can be formed on the electrodes of IC chips using a wedge bonder, the process is simple and bumps can be formed at low cost.
（２） ワイヤーボンダを用いた従来の方法に比較し
て、バンプの上面を平坦面に形成できるととも４にバン
プの高さを１０ｐｍ以下に形成することができる。した
がって、第３図に示すように、熱衝撃試験（１時間に一
５５°Ｃから１２５°Ｃに上げた後−５５°Ｃまで下げ
るのを１サイクルとする試験）で、バンプの高さ゛が２
０ｐｍのものは１００サイクルで不良率が１００％であ
ったが、バンプの高さを８ｐｍにしたものは３００サイ
クルでも不良率が５％、１００サイクルでは２％以下と
いう良好な結果であった。このように本発明の形成方法
で形成した１０１１ｍ以下のバンプを形成すると熱衝撃
試験の不良率を小さくすることが可能であるという効果
を有する。(2) Compared to the conventional method using a wire bonder, the upper surface of the bump can be formed into a flat surface, and the height of the bump can be formed to 10 pm or less. Therefore, as shown in Figure 3, in a thermal shock test (a test in which one cycle consists of raising the temperature from -55°C to 125°C in one hour and then lowering it to -55°C), the height of the bump was 2
The one with 0 pm had a defective rate of 100% after 100 cycles, but the one with a bump height of 8 pm had a good result of 5% defective even after 300 cycles and less than 2% after 100 cycles. As described above, when a bump with a length of 1011 m or less is formed by the forming method of the present invention, it is possible to reduce the defect rate in a thermal shock test.
（３） ウェッジボンダで金属細線を電極上に圧着さ
せるために平面から見て細長い形状となるバンプを放射
上に形成することができる。したがって、接着面積が大
きくとれるとともにコーテング樹脂の応力を逃すので強
固に接合され接点の信頼性が犬となる。(3) In order to pressure-bond a thin metal wire onto an electrode using a wedge bonder, a bump having an elongated shape when viewed from above can be formed radially. Therefore, a large bonding area can be obtained, and the stress of the coating resin is released, so that the bond is firmly bonded and the reliability of the contact point is excellent.
第１図は、本発明のバンプ形成方法を示す断面図、第２
図は、ＩＣチップの電極面を示す平面図、第３図は、Ｉ
Ｃチップの加熱サイ
相関々係を示すグラフである。
１・・・・・・ウェッジポンダ
３・・・・・・金属細線
７・・・・・・バンプ
タル数と不良率の
２・・・・・・ＩＣチップ
５・・・・・・電極FIG. 1 is a sectional view showing the bump forming method of the present invention, and FIG.
The figure is a plan view showing the electrode surface of the IC chip, and FIG.
It is a graph showing the correlation between the heating temperature and the temperature of the C chip. 1...Wedge ponder 3...Metal thin wire 7...Bumptal number and defective rate 2...IC chip 5...Electrode
Claims (2)
い形状で上面が平坦面を有し、高さが １０μｍ以下のバンプをＩＣチップの中心に向かって放
射状に配列させたことを特徴とするフ リップチップ用ＩＣ。(1) Thin metal wires are crimped onto the electrodes of the IC chip to form elongated shapes with flat top surfaces, and bumps with a height of 10 μm or less are arranged radially toward the center of the IC chip. IC for flip chip.
属細線を圧着して接合する工程と、前記接合した金属細
線の端部をカットする工程からなるフリップチップ用Ｉ
Ｃのバンプ形成方法。(2) I for flip chips, which consists of a step of crimping and bonding a thin metal wire onto the electrode part of an IC chip using a wedge bonder, and a step of cutting the end of the bonded thin metal wire.
Bump forming method of C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251769A JP2821777B2 (en) | 1989-09-29 | 1989-09-29 | Flip chip IC and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251769A JP2821777B2 (en) | 1989-09-29 | 1989-09-29 | Flip chip IC and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03116735A true JPH03116735A (en) | 1991-05-17 |
| JP2821777B2 JP2821777B2 (en) | 1998-11-05 |
Family
ID=17227646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1251769A Expired - Lifetime JP2821777B2 (en) | 1989-09-29 | 1989-09-29 | Flip chip IC and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2821777B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5077875A (en) * | 1990-01-31 | 1992-01-07 | Raytheon Company | Reactor vessel for the growth of heterojunction devices |
| US5441917A (en) * | 1992-07-17 | 1995-08-15 | Lsi Logic Corporation | Method of laying out bond pads on a semiconductor die |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9184144B2 (en) * | 2011-07-21 | 2015-11-10 | Qualcomm Incorporated | Interconnect pillars with directed compliance geometry |
-
1989
- 1989-09-29 JP JP1251769A patent/JP2821777B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5077875A (en) * | 1990-01-31 | 1992-01-07 | Raytheon Company | Reactor vessel for the growth of heterojunction devices |
| US5441917A (en) * | 1992-07-17 | 1995-08-15 | Lsi Logic Corporation | Method of laying out bond pads on a semiconductor die |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2821777B2 (en) | 1998-11-05 |
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