JPS6418247A - Plastic sealed semiconductor device - Google Patents

Plastic sealed semiconductor device

Info

Publication number
JPS6418247A
JPS6418247A JP62175335A JP17533587A JPS6418247A JP S6418247 A JPS6418247 A JP S6418247A JP 62175335 A JP62175335 A JP 62175335A JP 17533587 A JP17533587 A JP 17533587A JP S6418247 A JPS6418247 A JP S6418247A
Authority
JP
Japan
Prior art keywords
semiconductor chip
resin
reduced
container
amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62175335A
Other languages
Japanese (ja)
Inventor
Hirotoshi Kaneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62175335A priority Critical patent/JPS6418247A/en
Publication of JPS6418247A publication Critical patent/JPS6418247A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a characteristic from deteriorating by a method wherein the amount of a resin near a semiconductor chip is reduced partially so that a stress to be exerted on the semiconductor chip due to the resin can be reduced even when the chip is subjected to a heat cycle of a repeated heating and cooling operation. CONSTITUTION:A semiconductor chip 4 is supported on a base plate 1 of a container; external extraction terminals 6, 7 connected to the semiconductor chip 4 are extracted to an upper part of the container; this assembly is sealed by a resin 9 injected into the container 8. During this process, an amount of the resin near the semiconductor chip 4 is reduced partially. By this setup, even when a plastic-packaged semiconductor device is subjected to a heat cycle and the sealing resin 9 is expanded and contracted repeatedly, a stress to be exerted on the semiconductor chip 4 due to the resin 9 is reduced because the amount of the resin near the semiconductor chip 4 is little; accordingly, it is possible to prevent its characteristic from deteriorating.
JP62175335A 1987-07-14 1987-07-14 Plastic sealed semiconductor device Pending JPS6418247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62175335A JPS6418247A (en) 1987-07-14 1987-07-14 Plastic sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62175335A JPS6418247A (en) 1987-07-14 1987-07-14 Plastic sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6418247A true JPS6418247A (en) 1989-01-23

Family

ID=15994270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62175335A Pending JPS6418247A (en) 1987-07-14 1987-07-14 Plastic sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6418247A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009059923A (en) * 2007-08-31 2009-03-19 Mitsubishi Electric Corp Semiconductor device
CN102157400A (en) * 2011-01-30 2011-08-17 南通富士通微电子股份有限公司 Method for encapsulating high-integration wafer fan-out
US9324583B2 (en) 2011-01-30 2016-04-26 Nantong Fujitsu Microelectronics Co., Ltd. Packaging method
US20190229031A1 (en) * 2018-01-23 2019-07-25 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009059923A (en) * 2007-08-31 2009-03-19 Mitsubishi Electric Corp Semiconductor device
CN102157400A (en) * 2011-01-30 2011-08-17 南通富士通微电子股份有限公司 Method for encapsulating high-integration wafer fan-out
US9324583B2 (en) 2011-01-30 2016-04-26 Nantong Fujitsu Microelectronics Co., Ltd. Packaging method
US20190229031A1 (en) * 2018-01-23 2019-07-25 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing thereof
CN110071071A (en) * 2018-01-23 2019-07-30 三菱电机株式会社 The manufacturing method of semiconductor device and semiconductor device
JP2019129201A (en) * 2018-01-23 2019-08-01 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device
DE102019200271B4 (en) 2018-01-23 2022-09-29 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same

Similar Documents

Publication Publication Date Title
US4688152A (en) Molded pin grid array package GPT
CA1216117A (en) Transfer molding method and apparatus to carry out process
KR950704837A (en) METHOD OF FORMING INTERFACE BETWEEN DIE AND CHIP CARRIER
US5254501A (en) Same-side gated process for encapsulating semiconductor devices
JPS6418247A (en) Plastic sealed semiconductor device
JPS6457738A (en) Package for semiconductor device
JPS5591839A (en) Production of electronic parts
JPS57128930A (en) Resin sealing
JPS57112055A (en) Integrated circuit package
JPS54101668A (en) Ultrasonic wire bonding method
JPS5211866A (en) Resin sealing method in a semiconductor device
JPS5669846A (en) Sealing method of package
JPS634919A (en) Heat-compression molding device for plastic
JPS57159032A (en) Forming method for package of electronic timepiece
JPS57178352A (en) Manufacture of resin sealing type semiconductor device and lead frame employed thereon
GB1446739A (en) Method of manufacturing an integrated circuit device of the dual- in-line type
JPS554913A (en) Resin molding method
JPS5710955A (en) Manufacture of semiconductor device
JPS574132A (en) Manufacture of semiconductor device
JPS5720437A (en) Resin sealing metal mold for semiconductor device
JPS543469A (en) Resin sealing method for semiconductor device
JPS6430237A (en) Manufacture of resin-sealed semiconductor device
JPS5585037A (en) Bonding method
JPS6454752A (en) Pin grid array semiconductor package
JPS5385160A (en) Production of semiconductor device