GB1446739A - Method of manufacturing an integrated circuit device of the dual- in-line type - Google Patents

Method of manufacturing an integrated circuit device of the dual- in-line type

Info

Publication number
GB1446739A
GB1446739A GB5332473A GB5332473A GB1446739A GB 1446739 A GB1446739 A GB 1446739A GB 5332473 A GB5332473 A GB 5332473A GB 5332473 A GB5332473 A GB 5332473A GB 1446739 A GB1446739 A GB 1446739A
Authority
GB
United Kingdom
Prior art keywords
lead frame
pins
integrated circuit
bar
nov
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5332473A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
ATES Componenti Elettronici SpA
SGS ATES Componenti Elettronici SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATES Componenti Elettronici SpA, SGS ATES Componenti Elettronici SpA filed Critical ATES Componenti Elettronici SpA
Publication of GB1446739A publication Critical patent/GB1446739A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

1446739 Integrated circuits SGS ATES COMPONENTI ELETTRONICI SpA 16 Nov 1973 [16 Nov 1972] 53324/73 Heading H1K A heat sink for an integrated circuit comprises flat copper or aluminium bar 1 with two pins extending from ribs 4 on one surface thereof to a height which is initially greater than that of the eventual encapsulated package. The device is assembled by passing the pins through windows in a lead frame until it rests on shoulders 3, welding the silicon substrate of the I.C. to the bar 1 and applying encapsulant using a mould which compresses the pins to the level of the encapsulated body, thus ensuring that surface 6 of the heat sink is pressed against a mould surface and remains free from encapsulant. At the same time shoulders 3 are deformed to retain the lead frame. The silicon substrate may alternatively be secured to a cradle portion of the lead frame (Fig. 3, not shown) which portion is welded to the metal bar 1. A plurality of I.C.s may be processed in a batch operation.
GB5332473A 1972-11-16 1973-11-16 Method of manufacturing an integrated circuit device of the dual- in-line type Expired GB1446739A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT31713/72A IT974672B (en) 1972-11-16 1972-11-16 RARE BUILT-IN HEAT SINK IN INTEGRATED CIRCUITS WITH RESIN CONTAINER

Publications (1)

Publication Number Publication Date
GB1446739A true GB1446739A (en) 1976-08-18

Family

ID=11234262

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5332473A Expired GB1446739A (en) 1972-11-16 1973-11-16 Method of manufacturing an integrated circuit device of the dual- in-line type

Country Status (7)

Country Link
JP (1) JPS501660A (en)
DE (1) DE2357350C3 (en)
ES (1) ES420805A1 (en)
FR (1) FR2207356B1 (en)
GB (1) GB1446739A (en)
IT (1) IT974672B (en)
NL (1) NL7315711A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651328Y2 (en) * 1976-08-18 1981-12-01
FR2495376A1 (en) * 1980-12-02 1982-06-04 Thomson Csf Casing for power semiconductors - has base plate forming heat sink with semiconductors encapsulated hardened plastics material
IT1218271B (en) * 1981-04-13 1990-04-12 Ates Componenti Elettron PROCEDURE FOR THE MANUFACTURE OF PLASTIC CONTAINERS WITH THERMAL DISSIPATOR FOR INTEGRATED CIRCUITS AND COMBINATION OF MOLD AND DISSIPATORS USABLE WITH SUCH PROCEDURE

Also Published As

Publication number Publication date
IT974672B (en) 1974-07-10
JPS501660A (en) 1975-01-09
NL7315711A (en) 1974-05-20
DE2357350B2 (en) 1975-05-22
FR2207356B1 (en) 1976-11-19
FR2207356A1 (en) 1974-06-14
ES420805A1 (en) 1976-04-16
DE2357350C3 (en) 1980-01-24
DE2357350A1 (en) 1974-06-12

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee