JPS6417112A - Interface device - Google Patents

Interface device

Info

Publication number
JPS6417112A
JPS6417112A JP62173277A JP17327787A JPS6417112A JP S6417112 A JPS6417112 A JP S6417112A JP 62173277 A JP62173277 A JP 62173277A JP 17327787 A JP17327787 A JP 17327787A JP S6417112 A JPS6417112 A JP S6417112A
Authority
JP
Japan
Prior art keywords
signal
state
data
holding
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62173277A
Other languages
Japanese (ja)
Inventor
Motoyasu Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP62173277A priority Critical patent/JPS6417112A/en
Publication of JPS6417112A publication Critical patent/JPS6417112A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To surely transmit the data produced asynchronously with each other to a CPU just with a single reading action by holding the state of the data signal synchronized by a synchronizing circuit via a monitor circuit in the activating timing of a read signal and then delivering the held signal state in the form of data. CONSTITUTION:For instance, a data signal DT is activated in the timing as shown in a diagram and therefore a JKFF 7 is set at the rise of a system clock SCK. Then a chip selection signal CS1 and a read signal RD are produced. Thus an FF 8 is set and the holding state of an FF 7 is held by the FF 8. This holding state is transmitted to a CPU as a signal STD via a 3-state buffer 10 during an active period of the signal RD. Hereafter the buffer 10 is set under a high impedance state when the signal RD is inactivated. At the same time, the FF 7 is reset.
JP62173277A 1987-07-10 1987-07-10 Interface device Pending JPS6417112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173277A JPS6417112A (en) 1987-07-10 1987-07-10 Interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173277A JPS6417112A (en) 1987-07-10 1987-07-10 Interface device

Publications (1)

Publication Number Publication Date
JPS6417112A true JPS6417112A (en) 1989-01-20

Family

ID=15957466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173277A Pending JPS6417112A (en) 1987-07-10 1987-07-10 Interface device

Country Status (1)

Country Link
JP (1) JPS6417112A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5018979Y1 (en) * 1970-03-09 1975-06-10
JPS555101A (en) * 1978-06-05 1980-01-16 Nikkei Giken:Kk Casting method for wrapping metal
JPS601591U (en) * 1983-06-20 1985-01-08 小原金属工業株式会社 Arms for welding guns
JPS628938Y2 (en) * 1983-01-21 1987-03-02

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5018979Y1 (en) * 1970-03-09 1975-06-10
JPS555101A (en) * 1978-06-05 1980-01-16 Nikkei Giken:Kk Casting method for wrapping metal
JPS628938Y2 (en) * 1983-01-21 1987-03-02
JPS601591U (en) * 1983-06-20 1985-01-08 小原金属工業株式会社 Arms for welding guns

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