JPS5588148A - Test system of input-output control system - Google Patents

Test system of input-output control system

Info

Publication number
JPS5588148A
JPS5588148A JP16273978A JP16273978A JPS5588148A JP S5588148 A JPS5588148 A JP S5588148A JP 16273978 A JP16273978 A JP 16273978A JP 16273978 A JP16273978 A JP 16273978A JP S5588148 A JPS5588148 A JP S5588148A
Authority
JP
Japan
Prior art keywords
signal
slct
chc3
counter
mend
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16273978A
Other languages
Japanese (ja)
Other versions
JPS6032214B2 (en
Inventor
Seiichi Shimizu
Hatsuo Murano
Isao Sanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53162739A priority Critical patent/JPS6032214B2/en
Publication of JPS5588148A publication Critical patent/JPS5588148A/en
Publication of JPS6032214B2 publication Critical patent/JPS6032214B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to remove a logical fault in a stage of a trial manufacture test by generating an event, which occurs actually once or twice a month, at every minute by artificially increasing a load to an extreme independently of software by using an artificial channel.
CONSTITUTION: When FF16 is reset, a MRQ signal (memory request signal) is sent out. On receiving the MRQ signal, channel controller CHC3 sends a SLCT signl (selective signal) out. After sending the SLCT signal out, CHC3 reads the zero- address area of main memory 1 and when data are ready, a MEND signal (memory access end signal) is sent out to artificial channel 8. On reception of the MEND signal, the contents of counter 13 are increased by one. Since the MRQ signal is rising, CHC3 resends the SLCT signal and MEND signal out. When the value of counter 13 reaches its maximum value, a signal of "1" is generated on signal line l1 and the presence of the SLCT signal sets FF16 to change switch 15 over to the clock side, so that counter 13 will operate clocks.
COPYRIGHT: (C)1980,JPO&Japio
JP53162739A 1978-12-27 1978-12-27 Test method for input/output control system Expired JPS6032214B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53162739A JPS6032214B2 (en) 1978-12-27 1978-12-27 Test method for input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53162739A JPS6032214B2 (en) 1978-12-27 1978-12-27 Test method for input/output control system

Publications (2)

Publication Number Publication Date
JPS5588148A true JPS5588148A (en) 1980-07-03
JPS6032214B2 JPS6032214B2 (en) 1985-07-26

Family

ID=15760333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53162739A Expired JPS6032214B2 (en) 1978-12-27 1978-12-27 Test method for input/output control system

Country Status (1)

Country Link
JP (1) JPS6032214B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933524A (en) * 1982-08-20 1984-02-23 Fujitsu Ltd Overload control system
JPS60144851A (en) * 1983-12-30 1985-07-31 Fujitsu Ltd Channel controller
JPS62206648A (en) * 1986-03-07 1987-09-11 Fujitsu Ltd Overload test system
JP2006338484A (en) * 2005-06-03 2006-12-14 Sony Corp Bus loading test device and processing system with the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158809U (en) * 1987-04-08 1988-10-18

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933524A (en) * 1982-08-20 1984-02-23 Fujitsu Ltd Overload control system
JPS6252336B2 (en) * 1982-08-20 1987-11-05 Fujitsu Ltd
JPS60144851A (en) * 1983-12-30 1985-07-31 Fujitsu Ltd Channel controller
JPS62206648A (en) * 1986-03-07 1987-09-11 Fujitsu Ltd Overload test system
JPH0467220B2 (en) * 1986-03-07 1992-10-27 Fujitsu Ltd
JP2006338484A (en) * 2005-06-03 2006-12-14 Sony Corp Bus loading test device and processing system with the same

Also Published As

Publication number Publication date
JPS6032214B2 (en) 1985-07-26

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