JPS57101927A - Input/output circuit of microcomputer - Google Patents
Input/output circuit of microcomputerInfo
- Publication number
- JPS57101927A JPS57101927A JP55178334A JP17833480A JPS57101927A JP S57101927 A JPS57101927 A JP S57101927A JP 55178334 A JP55178334 A JP 55178334A JP 17833480 A JP17833480 A JP 17833480A JP S57101927 A JPS57101927 A JP S57101927A
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- gate
- signal
- case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
Abstract
PURPOSE:To raise a function of a microcomputer by a simple circuit configuration, by applying a pulse signal to a set terminal of a storage circuit through an AND gate controlled by a signal for switching a normal input and a latch input. CONSTITUTION:In case when data applied to input/output terminals a0-a3 is a normal input having a sufficiently long pulse period, a signal LIO becomes ''1'', an AND gate 10 is made conducting, and an operation as before is executed. On the other hand, in case when it is a latch input of data having a very short pulse, when data applied to the input terminals a0-a3 becomes ''1'' in a very short period in a state that a storage circuit 8 has been reset, this signal makes the circuit 8 a set state through an AND gate 12. Accordingly, ''1'' is stored in the circuit 8, and from an output Q, ''1'' is applied to an AND gate 11 through a buffer 9. In this case, when an input instruction is executed periodically, ''1'' stored in the circuit 8 stores ''0'' in the circuit 8 through a bus line 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55178334A JPS5942334B2 (en) | 1980-12-16 | 1980-12-16 | Microcomputer input/output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55178334A JPS5942334B2 (en) | 1980-12-16 | 1980-12-16 | Microcomputer input/output circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57101927A true JPS57101927A (en) | 1982-06-24 |
JPS5942334B2 JPS5942334B2 (en) | 1984-10-15 |
Family
ID=16046668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55178334A Expired JPS5942334B2 (en) | 1980-12-16 | 1980-12-16 | Microcomputer input/output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5942334B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61104114A (en) * | 1984-10-27 | 1986-05-22 | Mazda Motor Corp | Cylinder block structure of engine |
-
1980
- 1980-12-16 JP JP55178334A patent/JPS5942334B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5942334B2 (en) | 1984-10-15 |
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