JPS6432362A - Supervisory system for communication time - Google Patents

Supervisory system for communication time

Info

Publication number
JPS6432362A
JPS6432362A JP62189313A JP18931387A JPS6432362A JP S6432362 A JPS6432362 A JP S6432362A JP 62189313 A JP62189313 A JP 62189313A JP 18931387 A JP18931387 A JP 18931387A JP S6432362 A JPS6432362 A JP S6432362A
Authority
JP
Japan
Prior art keywords
buffer
data
output
mpu
circuit control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189313A
Other languages
Japanese (ja)
Inventor
Toshiaki Ihi
Isao Sasazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62189313A priority Critical patent/JPS6432362A/en
Publication of JPS6432362A publication Critical patent/JPS6432362A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To realize a communication time supervising system where a timer circuit for a circuit control system is simplified by using the buffer '0' outputted from a circuit control part every time the data is set from an MPU as the timing signals for circuit control. CONSTITUTION:A reset signal is supplied to an FF 16 from an MPU 12 and the output of the FF 16 is set at '0' every time the data is set at a transmission data buffer 11 from the MPU 12. In this case, the output of the FF 16 is quickly set by the output pulse of a load pulse generator 14 and equal to '1'. While the buffer 11 and a holding register 13 form a 2-story parallel buffer and the data supplied to the buffer 11 are quickly shifted to the register 13. Thus the output of the FF 16 rises up to '1' from '0'. Receiving this timing signal, the MPU 12 sets the next data at the buffer 11 and the output of the FF 16 is quickly reset to '0'. This reset state of the FF 16 is kept until the P/S conversion data is completely sent out of the register 13. In this case, the resetting time width of the FF 16 is constant and therefore this reset signal is used as a timer.
JP62189313A 1987-07-28 1987-07-28 Supervisory system for communication time Pending JPS6432362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189313A JPS6432362A (en) 1987-07-28 1987-07-28 Supervisory system for communication time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189313A JPS6432362A (en) 1987-07-28 1987-07-28 Supervisory system for communication time

Publications (1)

Publication Number Publication Date
JPS6432362A true JPS6432362A (en) 1989-02-02

Family

ID=16239262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189313A Pending JPS6432362A (en) 1987-07-28 1987-07-28 Supervisory system for communication time

Country Status (1)

Country Link
JP (1) JPS6432362A (en)

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