JPS5639630A - Pulse generating circuit for digital-analog conversion - Google Patents

Pulse generating circuit for digital-analog conversion

Info

Publication number
JPS5639630A
JPS5639630A JP11451879A JP11451879A JPS5639630A JP S5639630 A JPS5639630 A JP S5639630A JP 11451879 A JP11451879 A JP 11451879A JP 11451879 A JP11451879 A JP 11451879A JP S5639630 A JPS5639630 A JP S5639630A
Authority
JP
Japan
Prior art keywords
circuit
pulse
digital
generating circuit
set1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11451879A
Other languages
Japanese (ja)
Inventor
Masahiro Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11451879A priority Critical patent/JPS5639630A/en
Publication of JPS5639630A publication Critical patent/JPS5639630A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/82Digital/analogue converters with intermediate conversion to time interval

Abstract

PURPOSE:To remove an unrequired pulse generated in the generation timing period of a set input pulse, by preventing set and reset input pulses of a final-stage R-SFF circuit from being inputted at the same timing. CONSTITUTION:Set pulse set1 and RS1 detected by set input OR circuit 69 and reset input OR circuit 68 of final-stage R-SFF circuit 70 are prevented from being inputted to circuit 70 at the same timing. Namely, pulse set1 that corresponds to comparison signal CO1 is deleted by output RS2 of latch circuit 62 that selects output CO1 of comparator 53 and output COD of shift register 63. Thus, an unrequired pulse generated in the generation timing period of pulse set1 can be removed.
JP11451879A 1979-09-06 1979-09-06 Pulse generating circuit for digital-analog conversion Pending JPS5639630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11451879A JPS5639630A (en) 1979-09-06 1979-09-06 Pulse generating circuit for digital-analog conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11451879A JPS5639630A (en) 1979-09-06 1979-09-06 Pulse generating circuit for digital-analog conversion

Publications (1)

Publication Number Publication Date
JPS5639630A true JPS5639630A (en) 1981-04-15

Family

ID=14639751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11451879A Pending JPS5639630A (en) 1979-09-06 1979-09-06 Pulse generating circuit for digital-analog conversion

Country Status (1)

Country Link
JP (1) JPS5639630A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158325A (en) * 1984-08-29 1986-03-25 Shimadzu Corp D/a converter
US10568839B2 (en) 2011-01-11 2020-02-25 Capsugel Belgium Nv Hard capsules

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158325A (en) * 1984-08-29 1986-03-25 Shimadzu Corp D/a converter
US10568839B2 (en) 2011-01-11 2020-02-25 Capsugel Belgium Nv Hard capsules

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