JPS5534543A - Control input circuit - Google Patents

Control input circuit

Info

Publication number
JPS5534543A
JPS5534543A JP10676778A JP10676778A JPS5534543A JP S5534543 A JPS5534543 A JP S5534543A JP 10676778 A JP10676778 A JP 10676778A JP 10676778 A JP10676778 A JP 10676778A JP S5534543 A JPS5534543 A JP S5534543A
Authority
JP
Japan
Prior art keywords
variation
input
timer
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10676778A
Other languages
Japanese (ja)
Other versions
JPS5738076B2 (en
Inventor
Takeaki Yamaura
Hisashi Yamada
Etsuo Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10676778A priority Critical patent/JPS5534543A/en
Publication of JPS5534543A publication Critical patent/JPS5534543A/en
Publication of JPS5738076B2 publication Critical patent/JPS5738076B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C25/00—Arrangements for preventing or correcting errors; Monitoring arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Selective Calling Equipment (AREA)

Abstract

PURPOSE:To avoid reading of the erroneous information and thus to enhance the reliability for the data transmission device of the cyclic digital transmission system by setting the input information after the variation of the input signal becomes steady. CONSTITUTION:The variation is detected for input signals 5-7 via state variation detection circuit 13, and the output is applied to timing circuit 12 by actuation of timer 14. The output of timer 14 is set to the time during which the time dispersion of the input signals can be absorbed, and circuit 12 inhibits reed clock rcl to be applied to buffer memory 11 via the output of timer 14. In other words, the setting of the input is inhibited to memory 11 within a fixed time after occurrence of the state variation, and the input is set to memory 11 after the variation of the state becomes steady to be then delivered through parallel-serial conversion circuit 15. In such way, the reading of the erroneous information can be prevented.
JP10676778A 1978-08-31 1978-08-31 Control input circuit Granted JPS5534543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10676778A JPS5534543A (en) 1978-08-31 1978-08-31 Control input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10676778A JPS5534543A (en) 1978-08-31 1978-08-31 Control input circuit

Publications (2)

Publication Number Publication Date
JPS5534543A true JPS5534543A (en) 1980-03-11
JPS5738076B2 JPS5738076B2 (en) 1982-08-13

Family

ID=14442047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10676778A Granted JPS5534543A (en) 1978-08-31 1978-08-31 Control input circuit

Country Status (1)

Country Link
JP (1) JPS5534543A (en)

Also Published As

Publication number Publication date
JPS5738076B2 (en) 1982-08-13

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