JPS5592056A - Multiple line monitor system - Google Patents

Multiple line monitor system

Info

Publication number
JPS5592056A
JPS5592056A JP16524078A JP16524078A JPS5592056A JP S5592056 A JPS5592056 A JP S5592056A JP 16524078 A JP16524078 A JP 16524078A JP 16524078 A JP16524078 A JP 16524078A JP S5592056 A JPS5592056 A JP S5592056A
Authority
JP
Japan
Prior art keywords
memory
scnv
circuit
3mem1
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16524078A
Other languages
Japanese (ja)
Other versions
JPS5915584B2 (en
Inventor
Yoshifumi Toda
Kiyoaki Hodohara
Hideaki Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16524078A priority Critical patent/JPS5915584B2/en
Publication of JPS5592056A publication Critical patent/JPS5592056A/en
Publication of JPS5915584B2 publication Critical patent/JPS5915584B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Abstract

PURPOSE:To make it possible to monitor sufficiently a transmission quality with a comparatively simple constitution by writing each information from the I/O end of a speed converter circuit into a memory by the clock of an initialized phase and by reading it. CONSTITUTION:Speed converter circuit SCNV separates control pulses from a receiving signal, and parity check is performed by memory 3MEM1, etc., on a basis of the input signal of circuit SCNV. That is, each information is written from the I/O end of circuit SCNV into memory 3MEM1 and memory 3MEM2 by clocks of an initialized phase and is read, so that the transmission quality can be monitored sufficiently with a comparatively simple constitution.
JP16524078A 1978-12-31 1978-12-31 Multiple line monitoring device Expired JPS5915584B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16524078A JPS5915584B2 (en) 1978-12-31 1978-12-31 Multiple line monitoring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16524078A JPS5915584B2 (en) 1978-12-31 1978-12-31 Multiple line monitoring device

Publications (2)

Publication Number Publication Date
JPS5592056A true JPS5592056A (en) 1980-07-12
JPS5915584B2 JPS5915584B2 (en) 1984-04-10

Family

ID=15808524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16524078A Expired JPS5915584B2 (en) 1978-12-31 1978-12-31 Multiple line monitoring device

Country Status (1)

Country Link
JP (1) JPS5915584B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185489U (en) * 1984-11-10 1986-06-05

Also Published As

Publication number Publication date
JPS5915584B2 (en) 1984-04-10

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