JPS6415414U - - Google Patents
Info
- Publication number
- JPS6415414U JPS6415414U JP10942387U JP10942387U JPS6415414U JP S6415414 U JPS6415414 U JP S6415414U JP 10942387 U JP10942387 U JP 10942387U JP 10942387 U JP10942387 U JP 10942387U JP S6415414 U JPS6415414 U JP S6415414U
- Authority
- JP
- Japan
- Prior art keywords
- load resistors
- fet
- terminal
- stage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例を示す差動増幅器の
回路図、第２図は他の実施例を示す斜視図、第３
図は従来例を示す回路図である。
１……初段差動増幅ＦＥＴ、２……次段アンプ
、３……可変定電流回路、Ｔｐ１，Ｔｐ１′，Ｔ
ｐ２，Ｔｐ２′……端子。
FIG. 1 is a circuit diagram of a differential amplifier showing one embodiment of the present invention, FIG. 2 is a perspective view showing another embodiment, and FIG.
The figure is a circuit diagram showing a conventional example. 1... First-stage differential amplification FET, 2... Next-stage amplifier, 3... Variable constant current circuit, Tp 1 , Tp 1 ', T
p 2 , Tp 2 ′...terminal.
Claims (1)
抗を介して正電源側に接続され、ソース端子が共
通接続された一対のＦＥＴからなる初段差動ＦＥ
Ｔと、前記ソース端子に接続されたトランジスタ
（またはＦＥＴ）と第３の抵抗からなる可変定電
流回路と、前記初段差動ＦＥＴのドレインと前記
第１、第２の負荷抵抗の接続点のそれぞれが次段
のアンプに接続された差動増幅器において、前記
トランジスタのベース（またはＦＥＴのゲート）
と第３の負荷抵抗の間に定電流設定装置を接続す
るための端子を設けるとともに前記第１〜第３の
負荷抵抗のいずれかと前記電源間に初段電流測定
装置を接続するための端子を設けたことを特徴と
する差動増幅器。 The first stage differential FE consists of a pair of FETs whose drain terminals are each connected to the positive power supply side via the first and second load resistors, and whose source terminals are commonly connected.
T, a variable constant current circuit consisting of a transistor (or FET) and a third resistor connected to the source terminal, and connection points between the drain of the first stage differential FET and the first and second load resistors, respectively. is connected to the next stage amplifier, the base of the transistor (or the gate of the FET)
A terminal for connecting a constant current setting device is provided between the first to third load resistors and a third load resistor, and a terminal is provided for connecting a first stage current measuring device between one of the first to third load resistors and the power source. A differential amplifier characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10942387U JPS6415414U (en) | 1987-07-16 | 1987-07-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10942387U JPS6415414U (en) | 1987-07-16 | 1987-07-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6415414U true JPS6415414U (en) | 1989-01-26 |
Family
ID=31345650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10942387U Pending JPS6415414U (en) | 1987-07-16 | 1987-07-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6415414U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020608A (en) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | Differential amplifier circuit |
| JPS60233913A (en) * | 1984-05-07 | 1985-11-20 | Hitachi Ltd | Differential amplifier circuit |
-
1987
- 1987-07-16 JP JP10942387U patent/JPS6415414U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020608A (en) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | Differential amplifier circuit |
| JPS60233913A (en) * | 1984-05-07 | 1985-11-20 | Hitachi Ltd | Differential amplifier circuit |
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