JPS6412733A - Clock regeneration circuit - Google Patents
Clock regeneration circuitInfo
- Publication number
- JPS6412733A JPS6412733A JP62169492A JP16949287A JPS6412733A JP S6412733 A JPS6412733 A JP S6412733A JP 62169492 A JP62169492 A JP 62169492A JP 16949287 A JP16949287 A JP 16949287A JP S6412733 A JPS6412733 A JP S6412733A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- values
- cursor
- subtractor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To regenerate a clock signal with high accuracy from an input signal of four or more values, by providing a pre-cursor circuit, a differential outputting means, another adder, a discriminator, another delay circuit, a subtractor, a multiplier, an oscillator, and a sampling circuit. CONSTITUTION:When a 2B1Q signal of four values is inputted to an input terminal 20 as the input signal Si, it is sampled by the sampling circuit 24, and is delayed by one time slot T at the delay circuit 31 in a high-pass filter 30, and a difference to an original sampled signal is found by the subtractor 32, and is outputted as the signal of seven values. In the signal of seven values, intercode interference with a constant size is supplied to the signal before one time slot T by the pre-cursor circuit 40. Pre-cursor output is added on a delay signal S53 by the adder 51 in a discrimination decoding circuit 50, and is discriminated at a four value discriminator 52, and is sent to an output terminal 21. In such a way, it is possible to regenerate the clock signal phi with high accuracy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62169492A JPH0817376B2 (en) | 1987-07-07 | 1987-07-07 | Clock recovery circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62169492A JPH0817376B2 (en) | 1987-07-07 | 1987-07-07 | Clock recovery circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6412733A true JPS6412733A (en) | 1989-01-17 |
| JPH0817376B2 JPH0817376B2 (en) | 1996-02-21 |
Family
ID=15887530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62169492A Expired - Lifetime JPH0817376B2 (en) | 1987-07-07 | 1987-07-07 | Clock recovery circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0817376B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2020138327A1 (en) | 2018-12-27 | 2021-11-11 | 日揮ユニバーサル株式会社 | Ammonia decomposition catalyst and exhaust gas treatment method |
-
1987
- 1987-07-07 JP JP62169492A patent/JPH0817376B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0817376B2 (en) | 1996-02-21 |
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