JPS5734282A - Binary coded circuit for analog pulse train - Google Patents

Binary coded circuit for analog pulse train

Info

Publication number
JPS5734282A
JPS5734282A JP10955980A JP10955980A JPS5734282A JP S5734282 A JPS5734282 A JP S5734282A JP 10955980 A JP10955980 A JP 10955980A JP 10955980 A JP10955980 A JP 10955980A JP S5734282 A JPS5734282 A JP S5734282A
Authority
JP
Japan
Prior art keywords
pulse train
input terminals
clock
comparators
delayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10955980A
Other languages
Japanese (ja)
Inventor
Yoichiro Matsuura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Priority to JP10955980A priority Critical patent/JPS5734282A/en
Publication of JPS5734282A publication Critical patent/JPS5734282A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/01Details
    • G06K7/016Synchronisation of sensing process

Landscapes

  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Character Input (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To obtain a binary coded output with higher reliability through executing binary coding according to the comparison result in every pulse train, by an existing pulse train with comparing a pulse train delayed by one clock in an analog pulse train in every pulse train and by investigating the level change. CONSTITUTION:An analog pulse train Pn+1 synchronizing with clock pulses is generated from an image sensor and the pulse train Pn+1 is delayed by one clock in one clock delaying circuit 1. Further the delayed pulse train Pn is inputted kinto the first and second amplifiers 2, 3 respectively, for which a gain contant is signal discrimination. Further respective output signals alphaPn, betaPn from the amplifiers 2, 3 are applied to one input terminals of the first and second comparators 4, 5 and to the other input terminals of the first and second comparators 4, 5 and to the other input terminals the existing pulse train Pn+1 is applied to the other input terminals. Further both are compared with the comparators 4, 5 in every pulse train, and ''1'' or ''0'' is oututted according to larger or smaller value than the pre determined value, thereby permitting an FF10 to be controlled to execute binary coding, a binary coded output with higher reliability is generated.
JP10955980A 1980-08-08 1980-08-08 Binary coded circuit for analog pulse train Pending JPS5734282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10955980A JPS5734282A (en) 1980-08-08 1980-08-08 Binary coded circuit for analog pulse train

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10955980A JPS5734282A (en) 1980-08-08 1980-08-08 Binary coded circuit for analog pulse train

Publications (1)

Publication Number Publication Date
JPS5734282A true JPS5734282A (en) 1982-02-24

Family

ID=14513296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10955980A Pending JPS5734282A (en) 1980-08-08 1980-08-08 Binary coded circuit for analog pulse train

Country Status (1)

Country Link
JP (1) JPS5734282A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144076A (en) * 1983-12-30 1985-07-30 Toshiba Corp Binary-coding method of picture signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5218134A (en) * 1975-08-01 1977-02-10 Sumitomo Electric Ind Ltd Binary signal circuit of analog signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5218134A (en) * 1975-08-01 1977-02-10 Sumitomo Electric Ind Ltd Binary signal circuit of analog signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144076A (en) * 1983-12-30 1985-07-30 Toshiba Corp Binary-coding method of picture signal

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