JPS56140725A - Digital voltage-current converter - Google Patents

Digital voltage-current converter

Info

Publication number
JPS56140725A
JPS56140725A JP4440280A JP4440280A JPS56140725A JP S56140725 A JPS56140725 A JP S56140725A JP 4440280 A JP4440280 A JP 4440280A JP 4440280 A JP4440280 A JP 4440280A JP S56140725 A JPS56140725 A JP S56140725A
Authority
JP
Japan
Prior art keywords
circuit
binary code
offset current
code signal
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4440280A
Other languages
Japanese (ja)
Inventor
Masaharu Mizuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4440280A priority Critical patent/JPS56140725A/en
Publication of JPS56140725A publication Critical patent/JPS56140725A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To eliminate the occurrence of an offset or a drift and at the same time facilitate a formation for a semiconductor and an LSI, by adding the binary code signal to be supplied with the prescribed binary code signal that is obtained by giving a digital setting to the offset current. CONSTITUTION:An adder circuit 14, which adds the prescribed binary code signal that is obtained by giving a digital setting to the offset current of 4mA through the input setting part 15 and the output signal of the latch circuit 10, is provided between the circuit 10 which holds the binary code signals to be supplied in parallel and the D/A converter 18 having a dynamic range of 0-20mA. When no input is applied to the circuit 10, the circuit 14 delivers an offset current of 4mA. As a result, the D/A converter 13 transmits an output of 4-20mA.
JP4440280A 1980-04-03 1980-04-03 Digital voltage-current converter Pending JPS56140725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4440280A JPS56140725A (en) 1980-04-03 1980-04-03 Digital voltage-current converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4440280A JPS56140725A (en) 1980-04-03 1980-04-03 Digital voltage-current converter

Publications (1)

Publication Number Publication Date
JPS56140725A true JPS56140725A (en) 1981-11-04

Family

ID=12690510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4440280A Pending JPS56140725A (en) 1980-04-03 1980-04-03 Digital voltage-current converter

Country Status (1)

Country Link
JP (1) JPS56140725A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169734U (en) * 1982-05-07 1983-11-12 オムロン株式会社 DA converter output circuit
JPS6029045A (en) * 1983-06-30 1985-02-14 Fujitsu Ltd Digital/analog converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169734U (en) * 1982-05-07 1983-11-12 オムロン株式会社 DA converter output circuit
JPS6029045A (en) * 1983-06-30 1985-02-14 Fujitsu Ltd Digital/analog converter
JPH0425732B2 (en) * 1983-06-30 1992-05-01 Fujitsu Ltd

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