JPS56169479A - Clamp circuit - Google Patents

Clamp circuit

Info

Publication number
JPS56169479A
JPS56169479A JP7315980A JP7315980A JPS56169479A JP S56169479 A JPS56169479 A JP S56169479A JP 7315980 A JP7315980 A JP 7315980A JP 7315980 A JP7315980 A JP 7315980A JP S56169479 A JPS56169479 A JP S56169479A
Authority
JP
Japan
Prior art keywords
digital
level
circuit
clamp
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7315980A
Other languages
Japanese (ja)
Other versions
JPH028515B2 (en
Inventor
Masaaki Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7315980A priority Critical patent/JPS56169479A/en
Publication of JPS56169479A publication Critical patent/JPS56169479A/en
Publication of JPH028515B2 publication Critical patent/JPH028515B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE:To reduce the level jitter of clamp level remarkably, by adding a digital signal of a prescribed minute value at all times to a digital signal which is an error signal of clamp level to the reference level. CONSTITUTION:A digital level generating circuit 30 is a circuit producing a fine prescribed value of a digital signal, and a digital addition circuit 31 adds this digital signal and an error signal being the output of a digital subtraction circuit 18. Further, the level characteristic of this clamp circuit is the shift by digital value DELTAe for the output of the digital level generating circuit 30 toward the longitudinal direction. Thus, since the digital value DELTAe of the output of the digital level generating circuit is within one step of stairswise characteristic of comparison characteristic, this operation of the clamp circuit is the bang-bang control in which (Vp-Vpo) functions so as to converge to -DELTAV/2.
JP7315980A 1980-05-31 1980-05-31 Clamp circuit Granted JPS56169479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7315980A JPS56169479A (en) 1980-05-31 1980-05-31 Clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7315980A JPS56169479A (en) 1980-05-31 1980-05-31 Clamp circuit

Publications (2)

Publication Number Publication Date
JPS56169479A true JPS56169479A (en) 1981-12-26
JPH028515B2 JPH028515B2 (en) 1990-02-26

Family

ID=13510107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7315980A Granted JPS56169479A (en) 1980-05-31 1980-05-31 Clamp circuit

Country Status (1)

Country Link
JP (1) JPS56169479A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57206177A (en) * 1981-05-02 1982-12-17 Philips Nv Dc level control circuit for video signal
JPS58210761A (en) * 1982-06-01 1983-12-08 Nec Corp Clamping circuit
JPS60113586A (en) * 1983-11-24 1985-06-20 Nec Corp Clamping device
JPS62122379A (en) * 1985-11-21 1987-06-03 Nec Corp Video signal direct current restoration circuit
JPS63144761U (en) * 1987-03-13 1988-09-22
US7370247B2 (en) * 2005-09-28 2008-05-06 Intel Corporation Dynamic offset compensation based on false transitions

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57206177A (en) * 1981-05-02 1982-12-17 Philips Nv Dc level control circuit for video signal
JPS58210761A (en) * 1982-06-01 1983-12-08 Nec Corp Clamping circuit
JPS60113586A (en) * 1983-11-24 1985-06-20 Nec Corp Clamping device
JPS62122379A (en) * 1985-11-21 1987-06-03 Nec Corp Video signal direct current restoration circuit
JPS63144761U (en) * 1987-03-13 1988-09-22
JPH073730Y2 (en) * 1987-03-13 1995-01-30 ソニー株式会社 Clamp device
US7370247B2 (en) * 2005-09-28 2008-05-06 Intel Corporation Dynamic offset compensation based on false transitions

Also Published As

Publication number Publication date
JPH028515B2 (en) 1990-02-26

Similar Documents

Publication Publication Date Title
JPS56169479A (en) Clamp circuit
JPS5380132A (en) Signal control circuit
JPS5342659A (en) Semiconductor integrated circuit
EP0117357A3 (en) Digital signal composing circuits
JPS52142954A (en) Gain control circuit
JPS52119853A (en) Automatic phase control circuit
JPS57194378A (en) Test circuit of electronic clock
JPS5215371A (en) Electronic digital watch
JPS552927A (en) Automatic time correction device
JPS56140725A (en) Digital voltage-current converter
JPS57112129A (en) Latch circuit
JPS5341683A (en) Sampling control system
JPS5275236A (en) Signal processing circuit
JPS5750146A (en) Signal selector
JPS5352041A (en) Digital pll circuit
JPS57113101A (en) Fault-output preventing circuit of control circuit
JPS5582518A (en) Level adjuster
JPS52144948A (en) Gain control circuit
JPS52155576A (en) Input control circuit
JPS5352127A (en) Shutter control signal generating circuit
JPS52140780A (en) Electronic regulator
JPS5361956A (en) Automtic phase control circuit
JPS5365040A (en) Integrating circuit
JPS5499545A (en) Quantized noise formation circuit
JPS5784626A (en) Digital pll circuit