JPS5784626A - Digital pll circuit - Google Patents
Digital pll circuitInfo
- Publication number
- JPS5784626A JPS5784626A JP55161746A JP16174680A JPS5784626A JP S5784626 A JPS5784626 A JP S5784626A JP 55161746 A JP55161746 A JP 55161746A JP 16174680 A JP16174680 A JP 16174680A JP S5784626 A JPS5784626 A JP S5784626A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- inputted
- counter
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To increase the reliability against ambient temperature change and secular change, by digitizing all the circuit components in a PLL circuit. CONSTITUTION:A reference input signal 60 is inputted to a shaping circuit 601, and a timing input signal 103 being the output compares an A input data 101 being the comparison constant with a B input data 102 being the output of a counter 20, and outputs the result of comparison indicating lead/lag and coincidence from output lines 104, 105. When a timing maching circuit 50 detects the coincidence of outgoing phase in the inputs 104, 105, the counter 20 sequentially counts a signal 203 of an oscillator 70 and makes no phase correction. When a signal represeting the phase lag is inputted from the inputs 104, 105 to a circuit 50, a load signal 503 and a control signal 504 are generated, the addition constant data 401 from a selection circuit 403 is inputted to an adder 30, where it is added with the output of the counter 20, and the result is registered to the counter 20 from a load signal 503. When the phase is advanced, the subtraction constant is inputted to the adder 30 for correction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55161746A JPS5784626A (en) | 1980-11-17 | 1980-11-17 | Digital pll circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55161746A JPS5784626A (en) | 1980-11-17 | 1980-11-17 | Digital pll circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5784626A true JPS5784626A (en) | 1982-05-27 |
Family
ID=15741092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55161746A Pending JPS5784626A (en) | 1980-11-17 | 1980-11-17 | Digital pll circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5784626A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59122130A (en) * | 1982-12-28 | 1984-07-14 | Seiichi Miyazaki | Digital phase synchronization control circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5538800A (en) * | 1978-09-11 | 1980-03-18 | Raytheon Co | Digital freouency synthesizer |
JPS5567261A (en) * | 1978-11-15 | 1980-05-21 | Mitsubishi Electric Corp | Synchronizing clock generation circuit |
-
1980
- 1980-11-17 JP JP55161746A patent/JPS5784626A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5538800A (en) * | 1978-09-11 | 1980-03-18 | Raytheon Co | Digital freouency synthesizer |
JPS5567261A (en) * | 1978-11-15 | 1980-05-21 | Mitsubishi Electric Corp | Synchronizing clock generation circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59122130A (en) * | 1982-12-28 | 1984-07-14 | Seiichi Miyazaki | Digital phase synchronization control circuit |
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