JPS55118233A - Counting circuit - Google Patents

Counting circuit

Info

Publication number
JPS55118233A
JPS55118233A JP2528779A JP2528779A JPS55118233A JP S55118233 A JPS55118233 A JP S55118233A JP 2528779 A JP2528779 A JP 2528779A JP 2528779 A JP2528779 A JP 2528779A JP S55118233 A JPS55118233 A JP S55118233A
Authority
JP
Japan
Prior art keywords
preset
counter
count
intermediate frequency
counting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2528779A
Other languages
Japanese (ja)
Other versions
JPS6261173B2 (en
Inventor
Kenji Ichida
Yoshio Kachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2528779A priority Critical patent/JPS55118233A/en
Publication of JPS55118233A publication Critical patent/JPS55118233A/en
Publication of JPS6261173B2 publication Critical patent/JPS6261173B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/195—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To enable to correct the intermediate frequency, by controlling the enable signal to preset the preset counter, in the tuner using PLL circuit. CONSTITUTION:When the preset value N is preset to the preset counter 1, down count is made for the counter 1 with the clock CK, and when the content is ''4'', the output of the detection circuit 3 is at H level and it is fed to the selection circuit 2. The selection circuit 2 outputs the enable signal PE presetting the counter 1 when the counter 1 starts the count of ''1'' and the count of ''2'' and after counting ''1'', resulting that the preset values N, (N-1) and (N+1) are preset, allowing to change the intermediate frequency for correction.
JP2528779A 1979-03-05 1979-03-05 Counting circuit Granted JPS55118233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2528779A JPS55118233A (en) 1979-03-05 1979-03-05 Counting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2528779A JPS55118233A (en) 1979-03-05 1979-03-05 Counting circuit

Publications (2)

Publication Number Publication Date
JPS55118233A true JPS55118233A (en) 1980-09-11
JPS6261173B2 JPS6261173B2 (en) 1987-12-19

Family

ID=12161795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2528779A Granted JPS55118233A (en) 1979-03-05 1979-03-05 Counting circuit

Country Status (1)

Country Link
JP (1) JPS55118233A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177110A (en) * 1974-12-27 1976-07-03 Tokyo Shibaura Electric Co
JPS52125226A (en) * 1977-04-30 1977-10-20 Toshiba Corp Digital synthesizer receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177110A (en) * 1974-12-27 1976-07-03 Tokyo Shibaura Electric Co
JPS52125226A (en) * 1977-04-30 1977-10-20 Toshiba Corp Digital synthesizer receiver

Also Published As

Publication number Publication date
JPS6261173B2 (en) 1987-12-19

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