JPS5764192A - Electronic clock - Google Patents

Electronic clock

Info

Publication number
JPS5764192A
JPS5764192A JP13967780A JP13967780A JPS5764192A JP S5764192 A JPS5764192 A JP S5764192A JP 13967780 A JP13967780 A JP 13967780A JP 13967780 A JP13967780 A JP 13967780A JP S5764192 A JPS5764192 A JP S5764192A
Authority
JP
Japan
Prior art keywords
frequency
corrected
signal
error
place
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13967780A
Other languages
Japanese (ja)
Inventor
Takaharu Koba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13967780A priority Critical patent/JPS5764192A/en
Publication of JPS5764192A publication Critical patent/JPS5764192A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)

Abstract

PURPOSE:To adjust a clock to the least error condition by altering a frequency dividing ratio in accordance with an error or the error of precision of respective clocks. CONSTITUTION:An output signal of a reference oscillator 1 is input into a display 5 for time by way of a frequency dividor 2 and a counter 3. Now, as a ''reset to zero'' signal for second plate is so input into a terminal 9 as to be set by a time signal, then a counting value in a place for the second is retained in a retaining circuit 6 and the place for second in the counter 3 is reset. Further, the retained content is operated together with the corrected condition, which is corrected at the time when the former ''rest to zero'' signal for second place generated, through a operating circuit 7. Therefore, a frequency dividing ratio, which is to be corrected with a correcting circuit 11 for the frequency division, is controlled in accordance with the new corrected condition, thereby, the frequency dividing ratio of the frequency dividor 2 is altered.
JP13967780A 1980-10-06 1980-10-06 Electronic clock Pending JPS5764192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13967780A JPS5764192A (en) 1980-10-06 1980-10-06 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13967780A JPS5764192A (en) 1980-10-06 1980-10-06 Electronic clock

Publications (1)

Publication Number Publication Date
JPS5764192A true JPS5764192A (en) 1982-04-19

Family

ID=15250845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13967780A Pending JPS5764192A (en) 1980-10-06 1980-10-06 Electronic clock

Country Status (1)

Country Link
JP (1) JPS5764192A (en)

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