JPS5471924A - Binary circuit - Google Patents

Binary circuit

Info

Publication number
JPS5471924A
JPS5471924A JP13843577A JP13843577A JPS5471924A JP S5471924 A JPS5471924 A JP S5471924A JP 13843577 A JP13843577 A JP 13843577A JP 13843577 A JP13843577 A JP 13843577A JP S5471924 A JPS5471924 A JP S5471924A
Authority
JP
Japan
Prior art keywords
signal
signals
iii
amplitude
compared
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13843577A
Other languages
Japanese (ja)
Other versions
JPS5740700B2 (en
Inventor
Michiaki Miyagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP13843577A priority Critical patent/JPS5471924A/en
Publication of JPS5471924A publication Critical patent/JPS5471924A/en
Publication of JPS5740700B2 publication Critical patent/JPS5740700B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make video signals binary surely and stabilize the pulse width even in case of the fluctuation of input signals dependent upon various factors by performing the comparison processing near the middle point of the signal amplitude in the picture information processing.
CONSTITUTION: Output signal A from ITV 11 becomes voltage division signal I after amplification in 13, and signal II is obtained by delaying signal I, and signal II is obtained by delaying further signal I. The amplitude of signals I and III is made equal to each other, and the amplitude of signal II is set larger than that of signals I and III. Then, signals II and III are compared with each other in 16, and signals II and I are compared with each other in 18. Then, both comparison results C and D are operated to obtain AND of them in 20, and this AND output E becomes a final binary signal.
COPYRIGHT: (C)1979,JPO&Japio
JP13843577A 1977-11-19 1977-11-19 Binary circuit Granted JPS5471924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13843577A JPS5471924A (en) 1977-11-19 1977-11-19 Binary circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13843577A JPS5471924A (en) 1977-11-19 1977-11-19 Binary circuit

Publications (2)

Publication Number Publication Date
JPS5471924A true JPS5471924A (en) 1979-06-08
JPS5740700B2 JPS5740700B2 (en) 1982-08-30

Family

ID=15221902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13843577A Granted JPS5471924A (en) 1977-11-19 1977-11-19 Binary circuit

Country Status (1)

Country Link
JP (1) JPS5471924A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56140269U (en) * 1980-03-19 1981-10-23
JPH03179882A (en) * 1990-09-28 1991-08-05 Hamamatsu Photonics Kk Image pickup device picking up weak video image

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56140269U (en) * 1980-03-19 1981-10-23
JPH03179882A (en) * 1990-09-28 1991-08-05 Hamamatsu Photonics Kk Image pickup device picking up weak video image
JPH0566069B2 (en) * 1990-09-28 1993-09-21 Hamamatsu Photonics Kk

Also Published As

Publication number Publication date
JPS5740700B2 (en) 1982-08-30

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