JPS63164606A - Cyclic type digital filter - Google Patents

Abstract

PURPOSE:To prevent the oscillation to be caused by a limit cycle by providing a rounding means making an output of a multiplier circuit equal to have the same effective digits to those of the output of a delay circuit and allowing the rounding means to avoid rounding zero when a difference signal is not zero. CONSTITUTION:The rounding circuit 11 is a circuit rounding the difference signal being a twice value obtained from a multiplier circuit in the state of absolute value and when the absolute value of the input of the rounding circuit 11 is a minimum identification value of the delay circuit 8, the minimum identification value is outputted in the state of the absolute value, that is, the absolute value round-up is executed. An arithmetic circuit 12 is a circuit to correct a difference signal from the circuit 11 into a retarded output signal from the delay circuit 8, gives its output to an output terminal 7 and leads it to the delay circuit 8. The rounding by the rounding circuit 11 is executed by the truncation of the absolute value or the round-off in the absolute value state.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to recursive digital filters used to process sampled digital signals.

3. Background Art FIG. 3 is a block diagram showing an example of a conventional recursive digital filter. 1 is an input terminal into which a digital signal sampled at a sampling period T is input, and 2 is an output terminal. 3 is a delay circuit that delays the signal for a period of nT (n is a positive integer), 4 is a multiplication circuit that multiplies the signal obtained from delay circuit 3 by ia, and 6 is an input signal obtained from input terminal 1. This is an adder circuit that adds the output of the multiplier circuit 4 to the output terminal 2 and leads it to the output terminal 2 and the delay circuit 3.

The operation of the conventional recursive digital filter configured as described above will be explained using a two-conversion equation representing a discrete time system.

The transfer function in the conventional example shown in FIG. 3 can be expressed as H(z) in the following equation if two conversion equations are used.

= of H, −4□−・°°°“°°゛°゛°°°°°°(
In a cyclic digital filter as expressed by equation (1) and equation H(2), the stability of the system is guaranteed to be 1 to 1. The stability of the cyclic digital filter in this conventional example is guaranteed because the absolute value of the constant a by which the multiplier circuit 4 of FIG. 3 multiplies the signal is smaller than 1. To simplify the explanation, the constant a is assumed to be 0 (a (1). Therefore, the characteristics of this conventional example are O) Equation H
This is a well-known high-frequency suppression filter that suppresses the amplitude of high-frequency components. Further, in the case of a cyclic digital filter, the problem is the number of digits (number of bits) to transmit the signal. Since the output signal is fed back to the input side, a large number of digits is required for accuracy, but in terms of circuit scale, in digital signal processing, it is necessary to limit the number of digits of the signal by setting an appropriate number of significant digits. There must be. In the conventional example shown in FIG. 3, bits are limited for the output of the multiplier circuit 4 or the output of the adder circuit 6 which is added to the input signal obtained from the input terminal 1 by the adder circuit 6. Generally, bits are limited by rounding operations such as rounding off and truncating, but these two methods are effective because the circuit size required for the operations is small.

However, in the above configuration, even if the constant a of the multiplier circuit 4 is set in the range of O(a (1) and the system is stable, the bits of the signal Limit cycles may occur due to rounding errors that occur in the rounding operation that limits the number.This is because when a DC signal is input, the output signal converges as a DC signal with a DC gain of 1/1-a, but the past Due to the difference in the transient state of the delay circuit 6 depending on the signal series, the DC value at which the output signal converges may not always be constant.

As an example, a case will be explained in which the constant 8 of the multiplier circuit 4 is 0.76. If the input signal applied to the input terminal 1 is a DC signal with a signal value of 0 (unmanned state), the output signal must also be a DC signal with a signal value of 0. However, when the delay circuit 3 outputs a signal value 1 as a transient state due to the past signal string, the value added by the multiplier circuit 4 to the adder circuit 6 is 0.76. Further, when the delay circuit 3 outputs the transient state -1, the output of the multiplier circuit 4 becomes -0,75. In these cases, if the operation of rounding off the value below the decimal point in order to limit the number of bits of the output signal of the adder circuit 6 involves rounding, rounding down, or rounding up, a limit cycle occurs at a signal value of 1 or -1. Therefore, it is necessary to perform absolute value operations such as rounding off the absolute value and discarding the absolute value. Therefore, in a recursive digital filter like the conventional example shown in Fig. 3, if a high-pass filter that removes the DC component and extracts only the high-frequency component is configured in the preceding stage, the absolute value truncation can be used. Adding rounding operations can prevent limit cycles from occurring.

Next, a case will be described in which an input signal containing a DC component is applied to input terminal 1. The constant of the multiplier circuit 4 is set to 0.
．． 75, the DC gain is 171-a=4 as described above. Let us take as an example a case where a DC signal with a signal value of 1o is input to input terminal 1. When the delay circuit 3 outputs a signal value of 4° as a transient state, the multiplier circuit 4 outputs 3
0, the adder circuit 6 output does not require rounding operation, and D
The DC output signal value is determined to be 4o, which is 4 times the C gain. but,
1 when delay circuit 3 outputs signal value 39 as a transient state
The output of the multiplier circuit 4 is 29.25, so if you round off the absolute value as described above, the output signal will have a signal value of 39.
becomes.

As described above, in the cyclic digital filter as shown in FIG. 3, a limit cycle occurs even if the above-described operation of cutting off the absolute value is performed. Further, when n in the delay time nT of the delay circuit 3 is 2 or more, there is a possibility that n limit cycles will occur, so there will be no limit cycles with different signal values in a time-division manner, so-called This has the problem of causing an oscillation state.

In particular, this conventional filter is difficult to use for video signals that are constructed using a scanning method.

Compared to an acyclic digital filter, the limit cycle causes noise in the vertical direction on a flat screen, and the oscillation also causes noise in the horizontal direction, worsening the S/N of the image. However, there was a problem in that a cyclic digital filter with a small circuit scale could not be used.

In view of this, the present invention always outputs a DC signal with the same signal value for a DC signal with the same signal value, regardless of changes in the signal state due to the past signal train or the influence of noise, etc. It is an object of the present invention to provide a recursive digital filter that does not cause oscillation caused by limit cycles. , ゛Means for solving the problems The present invention provides a delay circuit for time-delaying output No. 6.

a subtraction circuit that extracts a difference signal between a delayed output signal and an input signal, a multiplication circuit that multiplies the difference signal by a predetermined ring number Kt, and adds or subtracts the difference signal multiplied by K to the delayed output signal. and a rounding means for rounding the multiplied difference signal to the same significant digits as the delayed signal, and not rounding to zero when the difference signal is not zero. 6. With a cyclic digital filter.
6. Effect The present invention has the above-described configuration, extracts a difference signal between an input signal and an output signal, and rounds the difference signal to correct it to an output signal, so that the rounding operation is performed without DC components. In addition to adding only the high frequency component to H, the above correction is performed as long as there is a difference between the input and output signals, so even if a DC signal is input, the limit 7
) does not cause a cycle.

Embodiment FIG. 1 shows a 1072 diagram of a cyclic digital filter in an embodiment of the present invention.

In FIG. 1, 6 is an input terminal into which a digital signal sampled at the sampling period τ is input, and 7 is an output terminal.

8 is a delay circuit that delays the signal for a period of nT; S is a subtraction circuit that subtracts the output of the delay circuit 8 from the input signal obtained from the input terminal 6 to extract a difference signal between the input signal and the output signal; (0 is a subtraction circuit); This is a multiplication circuit that multiplies the difference signal obtained from e by the busy multiplier.

Reference numeral 11 denotes a rounding circuit for rounding the double difference signal obtained from the multiplier circuit 1 in an absolute value state;
If the absolute value of one person's power is less than the minimum discrimination amount of the delay circuit 8, an operation of rounding up the absolute value is performed to output the minimum discrimination amount in the absolute value state. 12 is rounding circuit 1
1 is an arithmetic circuit which adds the difference signal obtained from 1 to the delayed output signal from the delay circuit 8 as a correction, and its output is sent to the output terminal 7 and also guided to the delay circuit 8.

The operation of the cyclic digital filter of this embodiment configured as described above will be explained below.

First, the transfer function G■ is expressed by the following equation using two conversion equations.

From equation (2), the stability of the system is guaranteed by 1l-Kl (1, but to simplify the explanation, o<1-K<1-1ll
OKKUKKU1. Therefore, the characteristics of this embodiment are as follows: (1) The gain is 1, and the filter is a high-frequency suppressing filter that suppresses the amplitude of high-frequency components. Next, the transfer function G' (4) for the input signal of the difference signal which is output from the multiplier circuit 1o, that is, passes through the rounding circuit 11 and is corrected to an output signal by the arithmetic circuit 12, is as follows.

This "(Z) has the characteristics of a high-pass filter (referred to as HPF) that removes direct current components.The adder circuit 12 in the subsequent stage
Since the loop configuration consisting of the delay circuit 8 and the delay circuit 8 operates as an integrating circuit, the input signal is reproduced by integrating the difference signal between the input and output extracted at "(Z)" in the subsequent stage. The time reproducibility is determined by the multiplier K of the multiplier circuit 10.
Determined by K.

The closer the multiplier K is to 0, the steeper the change, and the worse the reproducibility of high-frequency components.
The closer to 1, the smaller the high frequency suppression ratio becomes, and when the multiplier K is set to 1, the filter has a characteristic that allows the entire band to pass through (dynamic G(Z)).

In this embodiment, which operates as described above, the limit cycle will be explained next. The multiplier circuit 1° output is the above ('
Since it has HPF characteristics as shown in 42G'(z), if a DC signal is applied to the input, the output of the multiplier circuit 1o converges to the signal value 0 regardless of the signal value. Therefore, in order to limit the bits of the signal that must be performed by the integrating circuit at the subsequent stage, the output of the multiplication circuit 1o has no DC component, so it is sufficient to round it in an absolute value state. Therefore, the rounding operation performed by the rounding circuit 11 is performed by truncating the absolute value or rounding off the absolute value.

However, it is a matter of course that the signal digit to be rounded matches the least significant digit of the delay circuit output which is one input of the adder circuit 12. However, if the absolute value of the output of the multiplier circuit 10 is less than the minimum discrimination amount that can be represented by the significant digits of the output of the delay circuit 8, the output of the rounding circuit 11 is not set to 0 by rounding or rounding in the absolute value state. , outputs the value of the minimum discrimination amount. Accordingly, as long as the difference signal obtained by the subtraction circuit 9 does not become 0, the output signal is corrected, so that the values of the input and output signals completely match and no limit cycle occurs.

As described above, according to this embodiment, a cyclic filter is configured by sending the difference signal between the input signal and the output signal to the subsequent loop configuration, and the rounding operation for the difference signal is performed on the input signal and the output signal. By not outputting a zero value unless they completely match, it is possible to prevent a limit cycle from occurring regardless of the value of the input DC signal and the transient state of the signal due to the past signal string.

In this embodiment, the rounding circuit 11 is provided between the multiplication circuit and the addition circuit 12, but when an arithmetic operation is required in the rounding operation, it is possible to perform that operation in the arithmetic circuit 12 at the subsequent stage. Since the circuit 1o can be configured with a bit shift or addition/subtraction circuit, the calculations necessary for rounding operations can be performed using the multiplication circuit 1o.
FIG. 2 shows a second embodiment of the present invention, and its characteristics are exactly the same as the characteristics ((2J2G(4)) of the embodiment in FIG. The only difference from the embodiment in FIG. 1 is the input polarity of the subtraction circuit 13 and the arithmetic circuit 14, so the other components are given the same element numbers as in the embodiment in FIG.

When the subtraction circuit 13 extracts the difference signal between the input signal and the delayed output signal, the delayed output signal (output of the delay circuit 8) is used.
K to subtract the input signal obtained from input terminal 1 from .

The difference signal is extracted with a polarity opposite to that in the embodiment of FIG. Therefore, the arithmetic circuit 14 subtracts the output of the rounding circuit 11 from the output of the delay circuit 8 in order to add the rounded difference signal to the output signal side as a correction. The configuration of this embodiment can be implemented more easily than the embodiment of FIG. 1 if the polarity of the signal is taken into account. The operation will be explained below.

Since the DC gain of this embodiment is 1 from the above-mentioned @)2G(Z), the dynamic ranges of the input signal and the output signal are equal. Therefore, the dynamic range of the output of the delay circuit 8, which simply delays the output signal, is also equal.

Therefore, the digits by which the output of the delay circuit 8 increases in accuracy compared to the input signal are all digits less than the effective digits of the input signal. Therefore, when extracting the difference signal between the input signal and the output of the delay circuit 8, if the input polarity is set to subtract the input signal from the output of the delay circuit 8 as in the subtraction circuit 9 of this embodiment, then the difference signal of the input signal out of the output of the delay circuit 8 can be set. There is no need to perform arithmetic operations on digits less than the effective digits, and they can be sent as they are to the multiplication circuit 10 at the next stage. However, the rounding circuit 11 in the latter stage performs rounding in the absolute value state, and the arithmetic circuit 14 (or the arithmetic circuit 12 in FIG. 1)
As mentioned above, the delay circuit 8 output and the rounding circuit 1
Since the number of digits of each output is the same, even if the input polarity is set as in the subtraction circuit 13 of this embodiment, the number of digits operated by each subsequent circuit does not change. Therefore, compared to the embodiment shown in FIG. 1, the present embodiment shown in FIG. 2 is effective because the circuit scale of the subtraction circuit 13 can be made smaller.

Also, when handling wideband signals such as video signals,
Since the sampling period T needs to be very short, it is very important and effective to reduce the number of calculation digits as described above, considering the calculation speed of the circuit.

As described in detail, according to the present invention, regardless of differences in transient states within the filter due to past signal sequences or the influence of noise, DC signals of the same signal value always have the same signal value. This is very effective since it is possible to realize a recursive digital filter that can output a DC signal and that does not cause limit cycles and signal oscillations caused by limit cycles. In particular, when used for video signals, a filter that does not generate vertical and horizontal noise caused by the limit cycle and the oscillation can be created using a cyclic digital filter, which has a much smaller circuit scale than an acyclic digital filter. Since it can be configured with filters, its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cyclic digital filter according to an embodiment of the present invention, FIG. 2 is a block diagram of a cyclic digital filter according to another embodiment of the present invention, and FIG. 3 is a block diagram of a conventional cyclic digital filter. It is a block diagram. 8...Delay circuit, 9.13...Subtraction circuit, 1°...Multiplication circuit, 11...Rounding circuit, 12.14... ...Arithmetic circuit.

Claims (4)

[Claims] (1) A delay circuit that takes a signal digitized with a sampling period T as an input signal and delays the signal for a period of nT (n is a positive integer), and a difference signal between the output of the delay circuit and the input signal. a subtraction circuit for extracting, a multiplication circuit for multiplying the output of the subtraction circuit by a predetermined multiplier, an arithmetic circuit that adds or subtracts the output of the multiplication circuit to the output of the delay circuit and leads it to the delay circuit, and the multiplication circuit. A cyclic digital filter comprising a rounding means for making the output of the circuit have the same significant digits as the output of the delay circuit, and wherein the rounding means does not round to zero when the difference signal is not zero. (2) The cyclic digital filter according to claim 1, wherein the rounding means is configured inside the multiplication circuit. (3) The cyclic digital filter according to claim 1, wherein the rounding means is arranged between the multiplication circuit and the arithmetic circuit. (4) The cyclic digital filter according to claim 1, wherein the rounding means is constituted by an arithmetic circuit.