JPS6412734A - Clock regeneration circuit - Google Patents

Abstract

PURPOSE:To regenerate a clock signal with high accuracy from an input signal of four or more values, by providing a pre-cursor circuit, a discriminator, a differential outputting means, a subtractor, another delay circuit, a multiplier, an oscillator, and a sampling circuit. CONSTITUTION:When a 2B1Q signal is supplied to an input terminal as the input signal Si, it is sampled by the sampling circuit 24, and is delayed by one time slot T at the delay circuit 31 in a high-pass filter 30, and a difference to an original sampled signal is found by the subtractor 32, and it is outputted as the signal of seven values. In the signal of the seven values, intercode interference with a constant size is given on the signal before one time slot T. Pre-cursor output is discriminated at a seven value discriminator 50, and is decoded to an original signal of four values at a decoder circuit 51, and a decoder signal So is outputted from an output terminal 21. In such a way, the clock signal (phi) with high accuracy can be regenerated.