JPS6410943B2 - - Google Patents

Info

Publication number
JPS6410943B2
JPS6410943B2 JP56150396A JP15039681A JPS6410943B2 JP S6410943 B2 JPS6410943 B2 JP S6410943B2 JP 56150396 A JP56150396 A JP 56150396A JP 15039681 A JP15039681 A JP 15039681A JP S6410943 B2 JPS6410943 B2 JP S6410943B2
Authority
JP
Japan
Prior art keywords
circuit
diffusion layer
impact ionization
type
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56150396A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5851558A (ja
Inventor
Shinichi Kunieda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56150396A priority Critical patent/JPS5851558A/ja
Publication of JPS5851558A publication Critical patent/JPS5851558A/ja
Publication of JPS6410943B2 publication Critical patent/JPS6410943B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP56150396A 1981-09-22 1981-09-22 Ｍｏｓ型半導体装置 Granted JPS5851558A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56150396A JPS5851558A (ja) 1981-09-22 1981-09-22 Ｍｏｓ型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56150396A JPS5851558A (ja) 1981-09-22 1981-09-22 Ｍｏｓ型半導体装置

Publications (2)

Publication Number Publication Date
JPS5851558A JPS5851558A (ja) 1983-03-26
JPS6410943B2 true JPS6410943B2 (enExample) 1989-02-22

Family

ID=15496060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56150396A Granted JPS5851558A (ja) 1981-09-22 1981-09-22 Ｍｏｓ型半導体装置

Country Status (1)

Country Link
JP (1) JPS5851558A (enExample)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5751738B2 (enExample) * 1973-12-27 1982-11-04
JPS5279787A (en) * 1975-12-26 1977-07-05 Toshiba Corp Integrated circuit device
JPS5518006A (en) * 1978-07-25 1980-02-07 Toshiba Corp Mos-type dynamic memory

Also Published As

Publication number Publication date
JPS5851558A (ja) 1983-03-26

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