JPS6395732A - Power-on reset signal generating circuit - Google Patents

Abstract

PURPOSE:To form a power-on reset signal generating circuit ensuring a long reset time by using the voltage division output of a power voltage as the charging voltage of a time constant circuit and using the voltage division output of the power voltage similarly as a voltage being the reference of a comparison so as to use a small capacitance. CONSTITUTION:A voltage divider comprising resistors 3-5 is connected between a power terminal 1 and a ground terminal 2, and a series connection circuit comprised of a resistor 6 and a capacitor 7, that is, a time constant circuit is connected between the connecting point of the resistors 3, 4 and the ground terminal 2. Then a connecting point between the resistor 6 and the capacitor 7 is connected to one input (positive phase input) of a voltage level comparator 8 and a connecting point between the resistors 4, 5 is connected to the other input (negative phase input). A voltage level comparator 8 is inverted when the charging voltage (c) of the capacitor 7 is higher than one (b) of voltage division outputs of the voltage divider and its level of an output terminal 9 is inverted from a low level to a high level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-on reset signal generation circuit, and in particular, the present invention relates to a power-on reset signal generation circuit, and in particular, a device that requires initial settings when the power is turned on secures a certain period of time after the power is turned on, and performs the initial settings within that time. The present invention relates to a power-on reset signal generation circuit that generates an initial setting signal for ending an operation and entering normal operation after a certain period of time.

Figure 3 shows a conventional power-on reset signal generating circuit. A resistive voltage divider consisting of resistors 11 and 12, a resistor 10 and a capacitor 7 are connected between the electric conductor 1 and the ground terminal 2.
and the series connection circuit are connected. And resistance 1
0 and the capacitor 7 is connected to one input (positive phase input) of the voltage level comparator 8, and the other input (
Input the divided voltage output of the voltage divider to the negative phase input). The voltage level comparator 8 is inverted when the charged ff1W voltage C of the capacitor 7 becomes higher than the divided voltage output, and the level of its output terminal 9 is inverted from a low level to a high level.

FIG. 4 is a time chart showing signals of various parts for explaining the operation of the conventional circuit shown in FIG. Power terminal 1
When the voltage a rises at time T1 as shown in (a) of the same figure, the divided voltage output rises quickly like the voltage a and becomes a constant divided voltage v3 as shown in (b) of the same figure. reach. On the other hand, the charging voltage C of the capacitor 7 follows the time constant determined by the resistor 10 and the capacitor 7, as shown in FIG.
Second ascension. , the power supply voltage a is 5 volts and the divided voltage v3
is determined by the resistors 1i11R1 and R2 of the resistor 11.12, and v3 = 5R1 (R1 + R2). Also, the charging voltage C is expressed as c = 5 (1-exp (-t/τ)), where τ is the time constant of the resistor 10 and the capacitor 7, so after the power is turned on at time 1, the charging voltage C is divided into voltage v
The time t2 until it exceeds 3 is t2=-τ・Ioge
(5-v3 ＞//!5. Therefore, the output voltage of the voltage level comparator 8 is at time T3 as shown in FIG. 4(C).
The power-on reset signal is obtained by inverting from low level to high level.

In the conventional power-on reset signal generation circuit described above,
During the time 12 from power-on until the output of the voltage level comparator is inverted, if the time constant τ is constant, the divided voltage is the voltage [ff
It can be made longer as it approaches l pressure. However, the integrated circuit comparators commonly used as voltage level comparators are capable of reducing at least one human power by 1 to 1 below the supply voltage.
, 5pol must be lowered to 1- or more. For this reason, there is a limit to increasing t2 only by varying the divided voltage, and therefore, it is necessary to increase the time constant, which has the disadvantage that the number of customers for capacitors must be greatly reduced.

OBJECTS OF THE INVENTION An object of the present invention is to provide a power-on reset signal generation circuit that can secure a long reset time using a small capacitance capacitor.

Composition of the invention.

According to the present invention, a voltage dividing circuit that divides a power supply voltage to generate first and second divided voltages; a time constant circuit that is charged by the first divided voltage; A power-on reset signal generation circuit 1q is characterized in that it has a level comparison circuit that generates a power-on reset signal by comparing the level of the charging voltage and the level of the second divided voltage.

Example Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. That is,
A voltage divider consisting of resistors 3, 4, and 5 is connected between power supply terminal 1 and ground terminal 2, and a series connection circuit of resistor 6 and capacitor 7 is connected between the connection point of resistors 3 and 4 and ground terminal 2. Connect the constant circuit. Then, connect the connection point between the resistor 6 and the capacitor 7 to one input (positive phase input) of the voltage level comparator 8, and connect the resistor 4 to the other input (negative phase input).
Connect the connection points of and 5. The voltage level comparator 8 is inverted when the charged voltage C of the capacitor 7 becomes higher than one of the divided voltage outputs of the voltage divider, and the level of its output terminal 9 is inverted from a low level to a high level.

FIG. 2 is a time chart showing signals of various parts for explaining the operation of this embodiment. That is, when the voltage a of the power supply terminal 1 rises at a time aq -r 1 as shown in FIG.
Similarly, it rises quickly and reaches a constant divided voltage v2. On the other hand, the charging voltage C of the capacitor 7 approaches the divided voltage ■1 according to a time constant determined by the resistor Fc6 and the capacitor 7, as shown in FIG.

When the power supply voltage a is 5 volts, the divided voltage V1. V2 is determined by the resistance values R3, R4, and R5 of resistors 3 and 4.5, and v 1 = 5 (R4+R5)/(R3+R
4+R5)v2-5 R5/(R3+R4+R5). In addition, the charging voltage C is expressed as c=v1 (1-ext) (-t/l), where the time constant of the resistor 6 and capacitor 7 is τ, so the charging voltage C after the power is turned on at time T1 is divided voltage v
The time t1 until it exceeds 2 is t1==-τ logo
(v1-v2)/v1. Therefore, the output voltage d of the voltage level comparator 8 is inverted from low level to high level at time T2, as shown in FIG. 2(C).

In this way, in this embodiment, the divided voltage v 1. which is the output of the voltage divider. Since v2 can be set arbitrarily, by bringing the divided voltage ■2, which is the negative phase input of the level comparator, close to the charging voltage v1 of the capacitor, which is the positive phase input of the level comparator, However, the value of time t1 can be increased. In other words, it is possible to secure a long reset period with a small capacitor.

In addition, even when using a commonly used integrated circuit comparator, the divided voltage
By lowering the voltage to 5 volts or more, a long reset period can be secured with a similarly small capacitor.

Effects of the Invention As described above, according to the present invention, the divided output of the power supply voltage is used as the charging N voltage of the time constant circuit, and the divided output of the power supply voltage is also used as the reference voltage for level comparison. Therefore, both voltage levels for level comparison can be lowered with respect to the power supply voltage, making it possible to operate satisfactorily even when using an integrated circuit comparator, and also allowing long resets using a small capacitor. This has the effect of making it possible to secure the period.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart showing voltage waveforms at various parts of the circuit of FIG. 1, FIG. 3 is a diagram showing an example of a conventional power-on reset signal generation circuit, and FIG. 4
The figure is a time chart showing voltage waveforms at various parts of the circuit of FIG. 3. Explanation of symbols for main parts 3 to 5... Voltage dividing resistor 6... Time constant resistor 7... Capacitor 8... Level comparator

Claims (1)

[Claims] a voltage dividing circuit that divides a power supply voltage to generate first and second divided voltages; a time constant circuit that is charged by the first divided voltage; and a level of the charging voltage by the time constant circuit; A power-on reset signal generation circuit comprising: a level comparison circuit that generates a power-on reset signal by comparing the level of the second divided voltage.