JPS62142421A - A/d conversion method and a/d convertor used for it - Google Patents

Abstract

PURPOSE:To remove DC offset contained in an input signal by extracting the polarity information containing DC component of an input signal and adding stable minute DC offset to the input signal and A/D converting, or giving the safety minute DC offset to a comparator to execute the A/D conversion. CONSTITUTION:The device is provided with a terminal to which the voltage of sampling data charged in a capacitor 409 and a reference voltage are inputted and a switch 401 that can add the charge of specified magnitude to the terminal of a comparator 404 that outputs a polarity signal and to which the voltage of the sampling data is inputted. Thereby, two times of polarity signal, i.e. the case where the charge of specified magnitude is added to the sampling data and the case where the charge is not added. Further, by providing a switch 410 that can switch the reference voltage and reference voltage level shifted by specific amount in the terminal of the comparator 404 to which the reference voltage is inputted, two times of polarity signals using the reference voltage of different magnitude can be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is a single-chip codec with a built-in band-limiting filter that is particularly suitable for integration into integrated circuits in a PCM codec that follows a companding law called the A-law. The present invention relates to an A/D conversion method and an A/D converter used therein.

(Prior Art) Conventionally, as a technique in this field, there is a technique that uses a single-chip codec AD converter that follows the A-companding law. The configuration will be explained below using figures.

FIG. 2 is a diagram showing an example of the configuration of a transmitting section of a single-chip codec.

The input signal to the analog input terminal 1 is band-limited by a bandpass filter (hereinafter abbreviated as BPF) 2, AD converted by an AD converter 3 having a sampling and hold function, and outputted to an output terminal 4 as a digital signal output. be done. The auto-zero circuit 5 is a circuit for zeroing out the DC offset voltage of the BPF 2 and the AD converter 3. FIG. 3 is a circuit diagram showing an example of the configuration of an AD converter that can realize the A companding law using a capacitor ladder (hereinafter abbreviated as C ladder) used in integrated circuits. In the temple map 201,
203 is a switch, 202 is a capacitor C1 to CB,
Main ladder consisting of switches 81 to S8, 204
is a comparator, 205 is a sub-ladder, and 207 is a control circuit.

First, the operation will be explained. sampling switch 20
1 to the 2 side, the main ladder reset switch 2θ3 is closed, and the input signal is sampled with the main ladder switches S1 to S8 connected to the 1 side. After that, by opening the main ladder reset switch 203 and switching the sampling switch 20 to the 1 side, the input signal is
It is held by C1 to C8. AD conversion is performed using the sequential comparison feedback method, which first performs S1 to S8 of the main ladder.
is on the "d" side, the comparator 204 determines the polarity of the input signal as positive or negative, and the switch 206 changes the polarity of the reference voltage (+vB, -VR) according to the polarity of the input signal. After deciding, the main ladder switches 81 to 81 are controlled by the ladder switch control signal of the control circuit 207.
AD conversion is performed sequentially by the combination of S8 and the output of the sub-ladder 205. In such an AD converter, if a DC offset voltage exists in the BPF 2 in FIG. 2 and the condenser 204 in FIG. 3, the AD conversion output will be distorted and characteristics will deteriorate. To prevent this, as shown in FIG. 2, an auto-zero circuit 5 is provided which integrates polarity information and applies negative DC feedback to the BPF.

Next, the conversion characteristics of the small signal region of the DA converter based on the A companding law AD will be explained below with reference to FIG. Figure 4 (,) is A
FIG. 3B is a diagram showing D conversion characteristics and (b) DA conversion characteristics.

The AD converter input and DA converter output values in FIG. 4 are values when the maximum input point is 4096. Figure 4 (,) is A
When the D converter input is in the range of 0 to 2, 10000000
, a conversion output of 10000001 in the range 2 to 4, and the same conversion output corresponding to each input range. In addition, Fig. 4(b) shows that when the DA converter has a human power of 10,000,000, the output is 1, which is 1,000,000.
1 indicates that a value of 3 is output, and the following similarly indicates that a converted output corresponding to each input is output. With such conversion characteristics, when there is no input signal, the AD converter only changes the polarity bit due to the noise (for example, white noise) in the BPF 2 comparator 204, and the result is 10000000 or ooooooo.
Outputs oo. When this signal is input to the DA converter, the DA converter output is +1. -1 is changed by the polarity of the noise. The noise input amplitude to the Tsumashi converter is
For example, even if the amplitude is in the range of +0.1 to -0.1, the DA conversion output has an amplitude of +1 to -1, which means that the noise is amplified. This phenomenon does not occur because the polarity bit is fixed when there is no auto-zero circuit 5 in FIG. 2 and there is a DC offset inherent in the output of the MOBPF 2 or the comparator 2θ4 of the AD section.

(Problems to be Solved by the Invention) However, the removal of the auto-zero circuit causes deterioration of AD conversion characteristics due to fluctuations in the DC offset of the BPF and the condenser due to changes in the external environment such as power supply voltage and temperature. On the other hand, as mentioned earlier, the introduction of an auto-zero circuit has the problem of increasing the amount of noise when no signal is input.

The present invention provides an AD converter according to the A companding law,
The DC offset of BPF or fan ie generator is A
The purpose of the present invention is to provide an A/D conversion method that eliminates the influence on D conversion characteristics, does not increase noise when no signal is input, is suitable for integrated circuits, and has excellent performance, and an A/D converter used therein. do.

(Means for Solving the Problem) This invention provides an A
In a D converter, means for generating a minute and stable DC offset, determination of the polarity bit used for auto-zero when integrating the polarity bit of the input signal and performing auto-zero operation, and polarity bit output from the AD converter. This method is provided with means for separately making determinations.

(Function) The A/D conversion method of the present invention performs twice the step of outputting a polarity signal to the converter/mother circuit that compares the voltage of the sampling data with the reference voltage, and in one of the steps, one of the above voltages is output. By shifting the polarity by a predetermined voltage, the polarity signal can be kept to one side when no signal is input, regardless of white noise or the like.

Further, the A/D converter of the present invention has a converter/IP regulator that has terminals into which the voltage of the sampling data charged in the capacitor and the reference voltage are input, and outputs a polarity signal.
Since a switch is provided that can add a predetermined amount of charge to the terminal where the sampling data voltage is input, the polarity can be changed twice: when a predetermined amount of charge is added to the sampling data and when it is not. It can output signals.

Furthermore, another A/D conversion device of the present invention includes a comparator that has a terminal into which a voltage of sampling data charged in a capacitor and a reference voltage are input, and outputs a polarity signal.
The terminal to which the reference voltage is input is equipped with a switch that can switch between this reference voltage and a reference voltage shifted by a predetermined level from this reference voltage, so it is possible to generate two polarity signals using different reference voltages. It can be output.

(Embodiment) Fig. 1 (,) is a circuit diagram showing an embodiment of this invention, (b)
shows a time chart for explaining the circuit diagram.

In FIG. 1, the input terminal is the sampling switch 4
Connected to terminal 2 of 0, sampling switch, f401
Terminal 1 of is connected to GND (Ov), and terminal 3 is connected to terminal 1 of switches 81 to S8 of main ladder 402, which is comprised of capacitors 01 to C8 and switches S1 to S8. One end of the capacitors C1 to C8 of the main ladder 402 is connected to 81 to S8, respectively, and the other ends of the capacitors C1 to C8 are connected in common, and the main ladder reset switch 4
It is connected to terminal 1 of θ3 and input terminal 1 of comparator 404.

The terminals 2 of S1 to S8 of the main ladder 402 are commonly connected to the terminal 3 of the VR changeover switch 4θ6, and the terminals 3 of 87 to S8 are commonly connected to the output of the Saracider 405. Connector J with input terminal 2 connected to GND (OV)? The output of the regulator 404 is connected to the control circuit 407 and the input of the register 40g. V.

Terminals 1 and 2 of the changeover switch 406 are each +VR#
- Connected to VR. Capacitor 4 that realizes this invention
θ9, the switch 410 is connected to the capacitor 40 as shown in the figure.
90 one end is connected to input terminal 1 of comparator 404 and the other terminal is connected to terminal 3 of switch 410.
Terminal 1 is connected to GND, and terminal 2 is connected to +vR.

To explain the A/D conversion method in this configuration, first,
During the period from t1 to t2 shown in FIG. 1(b), the switch 40
1 to 2 side, switch 403 in ON state, switch 41
0 is connected to the 1 side, and the main ladder switches 81 to S8 are connected to the 1 side, the analog input signal is sampled, and the capacitors C1 to C8 of the main ladder 402 are charged as sampling data.

Next, during the period from t2 to t4 shown in FIG. 1(b), the switch 401 is set to the 1 side and the switch 403 is turned off. At this time, the switch 410, the switch 406, and the main ladder switches 81 to S8 do not change. In this state, a signal expressed by the following equation in which the polarity of the input signal voltage is inverted appears at the input terminal 1 of the comparator 404.

In this case, at the output of the comparator 404, a signal II I II or II OII appears, which indicates the polarity of the input signal.

Clock 1 in FIG. 1(b) included in the period from t2 to t4
Accordingly, the polarity signal of the input signal appearing at the output of the comparator 404 at time t3 is held in the register 408. The output signal of this register is sent to an auto-zero circuit to eliminate the DC offset voltage of the input signal and comparator 404, and is integrated and used as a correction voltage.

Next, during the period t4 to t6 shown in FIG. 1(b), the switch 4
10 is connected to the 2 side and a charge is added to the main ladder 402. At this time, the switches 401, 403, 406, and main ladder switches S1 to S8 do not change. In this state, the voltage at input terminal 1 of comparator 404 is as follows.

Here, vx is the same as vX in equation (1), and equation (2) is proportional to the input signal voltage, and the polarity of vx is inverted, regardless of the signal voltage or polarity. This means that the voltage level of VX is moved by adding a constant voltage (offset) shown in item 2 to vx.

Next, at time t5 included in the period t4 to t6 shown in FIG. The data is held in a register (not shown) included in the logic circuit 407. The output signal of this register is used as a control signal for the reference voltage ■R changeover switch 406, and is also used as a polarity bit of the AD conversion output signal. After selecting the reference voltage VR corresponding to the polarity of the voltage vx' which is the voltage vX proportional to the input signal voltage plus a certain offset in this way, successive comparison is performed after time t6 shown in FIG. Depending on the feedback method, main ladder switches 81 to S8
By switching, output of sub-ladder 405, etc.! Perform 1l AD conversion.

In an AD converter that operates in this way, the constant voltage shown in the second term on the right side of equation (2) above is taken as an example as shown in FIG.
a) CA so that the input value shown in the AD conversion characteristics is 1.
Set the O value. Now, if there is no signal at the AD converter input,
As mentioned above, after sampling the input signal, the
), the register 40B stores a polarity signal including the DC offset component of the input signal, sends it to the auto-zero circuit, integrates it, and outputs it to the BPF as an offset correction voltage.
Since the DC component in the input signal becomes zero. After memorizing the polarity of the input signal using clock 1, a predetermined constant voltage (value 1) is applied to CA. In order to obtain this value of 1, the capacitance of CA should be, for example, the same as the capacitor C1 having the minimum capacitance of the main ladder.

When the noise value vN when there is no input signal is -1〈VN〈1, by applying a constant voltage (value 1), the controller
The voltage at the input terminal 1 of the regulator 404 is shifted by the value 1, 0(V, (2), and the output of the commutator 404 does not change with a noise signal in this range. ~
When there is no signal input in the range of 1, the AD converter output is fixed at 10000000, and this
Even if A conversion is performed, only a DC output with a value of 1 is produced, and the noise is eliminated. In the case of a manned power signal, the signal is a signal with a DC offset of 1 added, but the DC offset included in the input signal is zeroed out by the auto-zero circuit, so the characteristics will not deteriorate due to the DC offset of 1. is so small that it can be ignored.

Above, we have explained the case where a charge is added to the sampling data during the second output of the polarity signal output by the commutator 404, which is performed twice. You may also remove it.

In this case, perform the following actions. When a positive or negative charge with a value of 1 is added to the sampling data as described above when outputting the polarity signal for the first time, the output polarity signal will have a value of 1.
This includes the DC offset of When this polarity signal is sent to the auto-zero circuit, it is integrated and fed back to the BPF as an offset correction voltage, so after several A/D conversion cycles, the origin of the sampling data charged in the capacitor will be the value 1. It will be shifted. Here, when outputting the polarity signal for the second time, the switch 410 is switched, the charge is removed and the voltage of the sampling data is shifted, and then the polarity signal is outputted.

The operation described above is the same in the second embodiment shown in FIG. In FIG. 5, instead of adding a stable offset to the input signal as explained in the first embodiment, the comparison voltage of the condenser is used to determine the polarity information including the DC offset of the input signal. , the comparison voltage of the converter is set to GND (0, V), and then the comparison voltage is switched to a stable reference bias voltage (for example, the same voltage as the value 1 explained in the first embodiment). Get results.

Note that although the capacitor ladder A/D converter has been described above, A/D conversion can be similarly performed in a resistor ladder A/D converter.

A resistor ladder A/D converter compares the sampling data filled in a capacitor with the voltage of the resistor ladder.

In such an A/D converter, charge can be added by moving the reference voltage of the resistor ladder, or by providing a switch that can add another capacitor, as in the capacitor ladder of the above embodiment. You should do it.

(Effects of the Invention) As described above in detail, according to the present invention, after extracting the polarity information including the DC component of the input signal, AD conversion is performed by adding a stable minute DC offset to the input signal, or Since AD conversion is performed by giving a stable minute DC offset to the comparator, the effect of removing the DC offset included in the input signal and the polarity noise due to white noise etc. when no signal is input can be expected.

[Brief explanation of drawings]

Figure 1 (,) is a circuit diagram of an AD converter showing the first embodiment of the present invention, (b) is a time chart for explaining the circuit diagram, and Figure 2 is a diagram of the transmitting section of a single-chip codec. Figure 3 is a circuit diagram showing a configuration example of a conventional oil converter, Figure 4 (,) is a diagram showing return conversion characteristics, (b
) is a diagram showing DA conversion characteristics, and FIG. 5 is a circuit diagram of an AD converter showing a second embodiment of the present invention. 401... Sampling switch, 402... Main ladder, 403... Main ladder switch, 404
...Con A? later, 405...+7' later,
406... Selector switch, 407... Control circuit,
40B...Resistor, 409...Capacitor, 41
0...Switch. Procedural amendment export) 1. Indication of the case 1985 Patent Application No. 282099 2, Title of the invention - Width conversion method and A/1) converter used therein 3, Person making the amendment Relationship with the case Patent application Person (
Address: 105) 1-7-12 Toranomon, Minato-ku, Tokyo
Office (〒105) No. 12-12, 1-7 Toranomon, Minato-ku, Tokyo Contents of the amendment (1) In the fourth line of page 15 of the specification, the phrase ``When added with a negative charge,'' was replaced with ``a negative charge.'' When a charge is added, the correction is made as follows. (2) In the same book, page 17, line 14, "4o3...main ladder switch" is corrected to "403...main ladder reset switch". (3) Correct the drawing “Figure 1 (a)” as shown in the attached sheet. CAGTTCCCCAACTGGTACATCAGCA
CCTCTCAAGln Phe Pro As
n Trp Tyr Ile Scr Th
r Ser GlnGCAGAAACATGCC
CGTCTTCCTGGGAGGGACCAla G
lu Asn Met Pro Val P
he Leu Gly Gly ThrAAA
GGCGGCCAGGATATAACTGACTTCA
CCATGLys Gly Gly Gln
Asp Ile Thr Asp Phe
Thr' MetCAATTTGTGTCTTCCTA
AAGAGAGCTGTACCCCAGln Phe
Val Ser Ser GAGAGTCCTGT
GCTGAATGTGGACTCAATCCCTAGG
GCTGGCAGAAAGGGAACAGAAGGTT
TTTGAGTACGGCTATAGCCTGGACT
TTCCTGTTGTCTACACCAATGCCCA
ACTGCCTGCCTTAGGGTAGTGCTAA
GACGATCTCCTGTCCATCAGCCAGG
ACAGTCΔGCTCTCTCCTTTCAGGGC
CAATCCCAGCCCTTTTTGTTGAGCCA
GGCCTCTCTCTCTCACCTCTCCTACTC
ACTTAAAGCCCGCCTGACAGAAACC
AGGCCACATTTTGGTTCTAAGAAAC
CCTCCTCTGTCATTCGCTCCCACAT
TCTGATGAGCAACCGCTTCCCTATT
TATTTATTT-ATTTGTTTGTTTGTT
TTGATTCATTGGTCTAATTTATTCA
AAGGGGGGCAAGAAGTAGCAGTGTCT
GTAAAAGAGCCTACTTTTTTA-rTAG
CTATGGAATCAATTCAATTTGGACT
GGTGTGCTCTCTTTTAAATCAAGTCC
TTTAATTAAGACTGAAAATATATAA
GCTCAGATTATTTAAATGGGGAATAT
TTATAAAATGAGCAAATATCATACTG
TTCAATGGTTCTCCAAATAAAACTTCA
CTAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAΔAAA From the figure above, a region complementary to the synthetic probe exists at positions 312 to 371 from the 5' end (underlined in the figure), 75% homology to the base sequence derived from human codon usage frequency. In addition, when searching for the longest reading frame in the C DNA of pGIF-α, it was found to be the region from the 57th to the 771st from the 5' end, and the region from the 312nd to the 771st according to the codon frame. 37
The amino acid sequence corresponding to the first base sequence is natural G
It was completely identical to the N-terminal 20-amino acids of IF. This indicates that the C DNA of pGIF-α is CONA encoding the GIF precursor protein. From the above nucleotide sequence, it is identified that natural GIF is encoded by the nucleotide sequence 312 to 771 and is composed of 153 amino acids. This result is based on the physical properties (molecular weight, N
The results were consistent with the terminal amino acid sequence and constituent amino acid composition ratio). Based on the above results, the protein primary structure of native GIF determined is shown below.

Claims (3)

[Claims] (1) (a) sampling an analog signal input through a filter and charging a capacitor as sampling data; (b) a comparator that compares the voltage of the sampling data with a first reference voltage; outputting a first polarity signal of data; (c) feeding back the polarity signal to the filter through an auto-zero circuit; and (d) converting the voltage of the sampling data and the first reference voltage by the comparator. and (e) comparing the voltage of the sampling data with a second reference voltage whose polarity is defined based on the second polarity signal. By encoding, the voltages are compared in steps (b) and (d), and the voltages are compared in steps (b) and (d).
An A/D conversion method in which one of the voltages compared in one step is moved by a predetermined level relative to the corresponding voltage in the other step. (2) A capacitor is charged with an analog signal passed through a filter as sampling data, and a polarity signal of the sampling data is obtained by comparing the voltage of the sampling data input from one terminal with the reference voltage input from the other terminal. In an A/D converter according to the A companding law, which has a comparator that outputs a polarity signal and can feed back the polarity signal to the filter through an auto-zero circuit, An A/D converter in which a circuit that can vary the amount of charge by a predetermined amount is connected via a switch. (3) A capacitor is charged with the filtered analog signal as sampling data, and a polarity signal of the sampling data is obtained by comparing the voltage of the sampling data input from one terminal with the reference voltage input from the other terminal. In an A/D converter according to the A companding law, which has a comparator that outputs a polarity signal and can feed back the polarity signal to the filter through an auto-zero circuit, the terminal to which the reference voltage of the comparator is input is An A/D converter configured to be able to switch between a reference voltage and a reference voltage obtained by shifting the voltage level by a predetermined level with respect to the reference voltage.