JPS6390835U - - Google Patents
Info
- Publication number
- JPS6390835U JPS6390835U JP18648886U JP18648886U JPS6390835U JP S6390835 U JPS6390835 U JP S6390835U JP 18648886 U JP18648886 U JP 18648886U JP 18648886 U JP18648886 U JP 18648886U JP S6390835 U JPS6390835 U JP S6390835U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- external connection
- conductive
- film
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａおよびｂは本考案の一実施例の斜視図
およびＡ―Ａ断面図、第２図ａおよびｂは第１図
の実施例のフレシキブル配線板の平面図およびＢ
―Ｂ断面図、第３図ａおよびｂは従来の半導体集
積回路装置の一例の斜視図およびＣ―Ｃ断面図で
ある。 １，１０…外部接続用導電膜、２，１１…ケー
スリード、３…フレキシブル配線板、４，１２…
ケース基板、５，１３…集積回路チツプ、６…プ
リント配線導電膜、９…金属線。
およびＡ―Ａ断面図、第２図ａおよびｂは第１図
の実施例のフレシキブル配線板の平面図およびＢ
―Ｂ断面図、第３図ａおよびｂは従来の半導体集
積回路装置の一例の斜視図およびＣ―Ｃ断面図で
ある。 １，１０…外部接続用導電膜、２，１１…ケー
スリード、３…フレキシブル配線板、４，１２…
ケース基板、５，１３…集積回路チツプ、６…プ
リント配線導電膜、９…金属線。
Claims (1)
- 周辺部に外部接続容導体膜を有する集積回路チ
ツプと、中央部に前記集積回路チツプを搭載し、
周辺部にケースリードを有するケース基体と、可
撓性と絶縁性とを有する薄板材料により形成され
た基材上に前記外部接続用導電膜と同じ数で同一
ピツチに配設されたプリント配線導電膜を有する
フレシキブル配線板とを備え、前記プリント配線
導電膜の内方の端部を前記外部接続用導電膜に接
続し、その外方の端部を前記ケースリードに接続
したことを特徴とする半導体集積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18648886U JPS6390835U (ja) | 1986-12-02 | 1986-12-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18648886U JPS6390835U (ja) | 1986-12-02 | 1986-12-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390835U true JPS6390835U (ja) | 1988-06-13 |
Family
ID=31136089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18648886U Pending JPS6390835U (ja) | 1986-12-02 | 1986-12-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390835U (ja) |
-
1986
- 1986-12-02 JP JP18648886U patent/JPS6390835U/ja active Pending