JPS6389249U - - Google Patents
Info
- Publication number
- JPS6389249U JPS6389249U JP18349686U JP18349686U JPS6389249U JP S6389249 U JPS6389249 U JP S6389249U JP 18349686 U JP18349686 U JP 18349686U JP 18349686 U JP18349686 U JP 18349686U JP S6389249 U JPS6389249 U JP S6389249U
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- semiconductor device
- protection film
- inclined surface
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案半導体装置の一実施例の要部を
示す断面図、第２図、第３図、第４図及び第５図
は夫々アルミニウム配線層に傾斜面を形成する工
程を示す線図、第６図は従来の半導体装置の一例
の要部を示す断面図、第７図及び第８図は夫々第
６図例の説明に供する線図である。
１はＰ型シリコン基板、２は絶縁層、３はアル
ミニウム配線層、４は表面保護膜、５はエポキシ
樹脂、１５，１６は夫々傾斜面である。
FIG. 1 is a cross-sectional view showing a main part of an embodiment of the semiconductor device of the present invention, and FIGS. 2, 3, 4, and 5 are lines showing the steps of forming an inclined surface on an aluminum wiring layer, respectively. 6 are cross-sectional views showing essential parts of an example of a conventional semiconductor device, and FIGS. 7 and 8 are diagrams for explaining the example shown in FIG. 6, respectively. 1 is a P-type silicon substrate, 2 is an insulating layer, 3 is an aluminum wiring layer, 4 is a surface protection film, 5 is an epoxy resin, and 15 and 16 are inclined surfaces, respectively.
Claims (1)
護膜とを有すると共に樹脂により封止された半導
体装置において、 上記配線層の縁部を傾斜面としたことを特徴と
する半導体装置。[Claims for Utility Model Registration] A semiconductor device having a wiring layer on a semiconductor substrate and a surface protection film covering the wiring layer and sealed with resin, in which the edge of the wiring layer is an inclined surface. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18349686U JPS6389249U (en) | 1986-11-28 | 1986-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18349686U JPS6389249U (en) | 1986-11-28 | 1986-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6389249U true JPS6389249U (en) | 1988-06-10 |
Family
ID=31130286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18349686U Pending JPS6389249U (en) | 1986-11-28 | 1986-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6389249U (en) |
-
1986
- 1986-11-28 JP JP18349686U patent/JPS6389249U/ja active Pending
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