JPS62112149U - - Google Patents
Info
- Publication number
- JPS62112149U JPS62112149U JP20266685U JP20266685U JPS62112149U JP S62112149 U JPS62112149 U JP S62112149U JP 20266685 U JP20266685 U JP 20266685U JP 20266685 U JP20266685 U JP 20266685U JP S62112149 U JPS62112149 U JP S62112149U
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- wiring film
- semiconductor device
- integrated circuit
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 5
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図ａはこの考案の一実施例における構造を
示す平面図、第１図ｂは第１図ａに示すもののＡ
―Ａ′断面における構造を示す断面図である。
１……半導体基板、２，３……アルミ配線膜、
４……スクライブライン、５……絶縁層保護膜。
Figure 1a is a plan view showing the structure of one embodiment of this invention, and Figure 1b is an A of the structure shown in Figure 1a.
- FIG. 2 is a cross-sectional view showing the structure in the A′ cross section. 1... Semiconductor substrate, 2, 3... Aluminum wiring film,
4...Scribe line, 5...Insulating layer protective film.
Claims (1)
装置において、集積回路チツプの主面上の周辺部
に配設された金属配線膜とスクライブライン間の
少なくとも前記集積回路チツプの各コーナ部に前
記金属配線膜に並列に別個の金属配線膜を設けた
ことを特徴とする半導体装置。 (2) 別個の金属配線膜が周辺部に配設された金
属配線膜に連結されていることを特徴とする実用
新案登録請求の範囲第１項記載の半導体装置。[Claims for Utility Model Registration] (1) In a semiconductor device formed by resin-sealing an integrated circuit chip, at least the above-mentioned area between the metal wiring film disposed in the peripheral area on the main surface of the integrated circuit chip and the scribe line. A semiconductor device characterized in that a separate metal wiring film is provided in parallel to the metal wiring film at each corner of an integrated circuit chip. (2) The semiconductor device according to claim 1, wherein a separate metal wiring film is connected to a metal wiring film disposed at the periphery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20266685U JPS62112149U (en) | 1985-12-28 | 1985-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20266685U JPS62112149U (en) | 1985-12-28 | 1985-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62112149U true JPS62112149U (en) | 1987-07-17 |
Family
ID=31167265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20266685U Pending JPS62112149U (en) | 1985-12-28 | 1985-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62112149U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163841A (en) * | 1983-03-08 | 1984-09-14 | Toshiba Corp | Resin sealed semiconductor device |
| JPS6018934A (en) * | 1983-07-13 | 1985-01-31 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
-
1985
- 1985-12-28 JP JP20266685U patent/JPS62112149U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163841A (en) * | 1983-03-08 | 1984-09-14 | Toshiba Corp | Resin sealed semiconductor device |
| JPS6018934A (en) * | 1983-07-13 | 1985-01-31 | Hitachi Micro Comput Eng Ltd | Semiconductor device |