JPH01140834U - - Google Patents
Info
- Publication number
- JPH01140834U JPH01140834U JP1988036481U JP3648188U JPH01140834U JP H01140834 U JPH01140834 U JP H01140834U JP 1988036481 U JP1988036481 U JP 1988036481U JP 3648188 U JP3648188 U JP 3648188U JP H01140834 U JPH01140834 U JP H01140834U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- protective film
- insulating protective
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Description
第１図は本考案の一実施例の半導体集積回路の
断面図、第２図は別の実施例の半導体集積回路の
断面図、第３図は従来の半導体集積回路の断面図
である。
１…シリコン基板、２，２′…内部配線、３…
電極パツド、４…保護絶縁膜、５ａ〜５ｄ…多結
晶シリコン配線。
FIG. 1 is a cross-sectional view of a semiconductor integrated circuit according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor integrated circuit according to another embodiment, and FIG. 3 is a cross-sectional view of a conventional semiconductor integrated circuit. 1...Silicon substrate, 2,2'...Internal wiring, 3...
Electrode pad, 4...protective insulating film, 5a to 5d...polycrystalline silicon wiring.
Claims (1)
導体集積回路チツプにおいて、前記絶縁保護膜か
ら露出している電極パツド等の金属部分または、
およびチツプ周縁部と、集積回路の内部領域との
間に多結晶シリコン配線をめぐらしていることを
特徴とする半導体集積回路。 In a semiconductor integrated circuit chip whose surface is mostly covered with an insulating protective film, metal parts such as electrode pads exposed from the insulating protective film or
and a semiconductor integrated circuit, characterized in that a polycrystalline silicon wiring is routed between a chip periphery and an internal region of the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988036481U JPH01140834U (en) | 1988-03-18 | 1988-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988036481U JPH01140834U (en) | 1988-03-18 | 1988-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01140834U true JPH01140834U (en) | 1989-09-27 |
Family
ID=31263083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988036481U Pending JPH01140834U (en) | 1988-03-18 | 1988-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01140834U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0289321A (en) * | 1988-09-27 | 1990-03-29 | Sony Corp | Semiconductor device |
-
1988
- 1988-03-18 JP JP1988036481U patent/JPH01140834U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0289321A (en) * | 1988-09-27 | 1990-03-29 | Sony Corp | Semiconductor device |