JPS6310551U - - Google Patents
Info
- Publication number
- JPS6310551U JPS6310551U JP1986104312U JP10431286U JPS6310551U JP S6310551 U JPS6310551 U JP S6310551U JP 1986104312 U JP1986104312 U JP 1986104312U JP 10431286 U JP10431286 U JP 10431286U JP S6310551 U JPS6310551 U JP S6310551U
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- semiconductor substrate
- utility
- scope
- registration request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第1図〜第5図はそれぞれ本考案の実施例の断
面図、第6図は従来装置の一例の断面図である。
〈符号の説明〉、1……半導体基板、2……絶
縁膜、3……金属膜、4……表面保護膜、5……
金ワイヤ、6……中間膜、7……第2の金属膜、
8……バンプ、9……凹凸部、10……ポリシリ
コン膜、11……アルミ配線、12……絶縁膜、
13……凹部。
1 to 5 are sectional views of embodiments of the present invention, and FIG. 6 is a sectional view of an example of a conventional device. <Explanation of symbols> 1...Semiconductor substrate, 2...Insulating film, 3...Metal film, 4...Surface protection film, 5...
Gold wire, 6... Intermediate film, 7... Second metal film,
8... Bump, 9... Uneven portion, 10... Polysilicon film, 11... Aluminum wiring, 12... Insulating film,
13... Concavity.
Claims (1)
となる金属膜の表面に凹凸を形成したことを特徴
とする半導体装置。 A semiconductor device characterized in that a metal film serving as a bonding pad formed on a semiconductor substrate has irregularities formed on the surface thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986104312U JPS6310551U (en) | 1986-07-09 | 1986-07-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986104312U JPS6310551U (en) | 1986-07-09 | 1986-07-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6310551U true JPS6310551U (en) | 1988-01-23 |
Family
ID=30977690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986104312U Pending JPS6310551U (en) | 1986-07-09 | 1986-07-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6310551U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008537636A (en) * | 2005-03-01 | 2008-09-18 | エプコス アクチエンゲゼルシャフト | Brazeable joint and method for forming the joint |
WO2021240748A1 (en) * | 2020-05-28 | 2021-12-02 | 三菱電機株式会社 | Semiconductor device, method for producing same, and electric power converter |
-
1986
- 1986-07-09 JP JP1986104312U patent/JPS6310551U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008537636A (en) * | 2005-03-01 | 2008-09-18 | エプコス アクチエンゲゼルシャフト | Brazeable joint and method for forming the joint |
WO2021240748A1 (en) * | 2020-05-28 | 2021-12-02 | 三菱電機株式会社 | Semiconductor device, method for producing same, and electric power converter |