JPS6384013A - Manufacture of semiconductor crystal layer - Google Patents

Manufacture of semiconductor crystal layer

Info

Publication number
JPS6384013A
JPS6384013A JP22718586A JP22718586A JPS6384013A JP S6384013 A JPS6384013 A JP S6384013A JP 22718586 A JP22718586 A JP 22718586A JP 22718586 A JP22718586 A JP 22718586A JP S6384013 A JPS6384013 A JP S6384013A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
crystal layer
semiconductor crystal
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22718586A
Other languages
Japanese (ja)
Other versions
JPH0525384B2 (en
Inventor
Tomoyasu Inoue
井上 知泰
Toshihiko Hamazaki
浜崎 利彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP22718586A priority Critical patent/JPS6384013A/en
Publication of JPS6384013A publication Critical patent/JPS6384013A/en
Publication of JPH0525384B2 publication Critical patent/JPH0525384B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To form a semiconductor crystal layer having no crystal defect by covering the top of a semiconductor layer which becomes the semiconductor crystal layer with a high melting point metallic oxide film, and then melting and recrystallizing the semiconductor layer. CONSTITUTION:A silicon oxide film 12 is formed by a CVD method on a single crystal silicon substrate 11, and a polycrystalline silicon layer 13 is formed by a CVD method using a thermal decomposition of silane on the upper surface. Then, a ZrO2 layer 14, for example, is formed as a high melting point metallic oxide layer by a sputtering method thereon. A sample 10 formed in this manner is scanned with an energy beam 15, such as a scanning type electron beam 15 in a direction of an arrow in the figure, the layer 13 is sequentially melted, and recrystallized to form a single crystal silicon layer 13a. Thus, a silicon crystal layer having less crystal defect and high quality can be formed.

Description

【発明の詳細な説明】 一″−i7[発明の目的] ?i 最近、電子ビームやレーザービーム等のエネルギービー
ム照射によるアニール法やストリップヒータを用いたゾ
ーンメルト法等によりSo1層を形成する技術の開発が
盛んに行なわれている。
[Detailed Description of the Invention] 1''-i7 [Object of the Invention] ?i Recently, technology has been developed to form the So1 layer by an annealing method using energy beam irradiation such as an electron beam or a laser beam, a zone melt method using a strip heater, etc. is being actively developed.

このSol技術の目指すところはSOI上に2次元的に
集積回路を形成し、高速動作素子を製作すること、或い
は集積回路を多層に形成して3次元集積素子を製作する
ことである。
The goal of this Sol technology is to fabricate a high-speed operating device by forming an integrated circuit two-dimensionally on SOI, or to fabricate a three-dimensional integrated device by forming an integrated circuit in multiple layers.

801層の形成は通常、シリコン単結晶基板上に絶縁層
として8102層を形成し、その上に多結晶シリコン層
を堆積し、更にその上に保護膜として3102Mを堆積
したのち、上記し、たエネルギービームアニールやゾー
ンメルト法により多結晶シリコン層を溶融・再結晶化さ
せることにより、前記多結晶シリコン層を単結晶化させ
る方法が用いられている。しかしこの場合、再結晶化後
のシリコン層は完全な単結晶層とならず種々の方位の−
−−これを改良する方法として第4図に示す様な方法が
行なわれている。
The 801 layer is usually formed by forming the 8102 layer as an insulating layer on a silicon single crystal substrate, depositing a polycrystalline silicon layer on top of it, depositing 3102M as a protective film on top of it, and then following the steps described above. A method is used in which the polycrystalline silicon layer is made into a single crystal by melting and recrystallizing the polycrystalline silicon layer by energy beam annealing or zone melting. However, in this case, the silicon layer after recrystallization does not become a complete single crystal layer, but has -
--As a method to improve this, a method as shown in FIG. 4 has been used.

即ち、シリコン基板(40)上に開孔部(41)を持つ
絶縁層(42)を形成し、続いて多結晶若しくは非晶質
のシリコン層を前記絶縁層(42)及び開口部(41)
の全面に形成し、その上に保護用8102層(44)を
堆積した後、電子ビーム或いはレーザービーム等のエネ
ルギービーム(45)を図のBから矢印方向へ照射し、
溶融・再結晶化させて単結晶シリコンら縦方向及びそれ
に続いて横方向にエピタキシャル成長が進行しシリコン
基板(40)の結晶方位情報を絶縁rf;A(42)上
に成長する単結晶層に与えることができる。
That is, an insulating layer (42) having an opening (41) is formed on a silicon substrate (40), and then a polycrystalline or amorphous silicon layer is formed on the insulating layer (42) and the opening (41).
After depositing a protective 8102 layer (44) on the entire surface, an energy beam (45) such as an electron beam or a laser beam is irradiated in the direction of the arrow from B in the figure,
By melting and recrystallizing the single crystal silicon, epitaxial growth progresses in the vertical direction and then in the horizontal direction, giving crystal orientation information of the silicon substrate (40) to the single crystal layer growing on the insulating RF;A (42). be able to.

しかしながら、シリコン基板(40)と同一方位の単結
晶層は上記開孔部(41)からの距離が高々 100μ
m程度しか成長せず、それ以上の距離の領域ではこの方
法によっても亜結晶粒界や結晶粒界が発生する等の問題
があワた。
However, the distance from the opening (41) to the single crystal layer in the same orientation as the silicon substrate (40) is at most 100μ.
The growth is only about m, and in regions beyond this distance, problems such as subgrain boundaries and grain boundaries occur even with this method.

これら従来方法の根本的原因は第5図に示すように多結
晶若しくは非晶質シリコン層(4B)が溶融状態のシリ
コン層(47)である際に、その上下に隣接する5i0
2層(42) 、 (44)の一部が溶解し溶融シリコ
ン層(47)中の酸素濃度が高まりシリコン中の固溶限
界濃度を超えてしまうため、再結晶化する際に析出物が
生成し、それが結晶粒界発生につながるものと考えられ
る。この考察は、融点直下の固相シリコン中の酸素の固
溶限界は1.5〜3X10”’cm−3であり、通常の
Sol再結晶化層中第5図で示した保護用5102層(
44)の一部を開孔させる手法がり、Prolf’re
r et al、、Appl、 Phys。
The fundamental cause of these conventional methods is that when the polycrystalline or amorphous silicon layer (4B) is a molten silicon layer (47) as shown in FIG.
Part of the two layers (42) and (44) dissolves, increasing the oxygen concentration in the molten silicon layer (47) and exceeding the solid solution limit concentration in silicon, resulting in the formation of precipitates during recrystallization. However, this is thought to lead to the generation of grain boundaries. This consideration shows that the solid solubility limit of oxygen in solid silicon just below the melting point is 1.5 to 3X10''cm-3, and the protective 5102 layer shown in Figure 5 in the normal Sol recrystallized layer (
44) The method of drilling a part of the hole is Prolf're
r et al., Appl, Phys.

Lett、 47(1985057,に提案されている
。これは溶融したシリコン層中に含まれている過剰な酸
素原子がシリコン原子と結合した一酸化シリコン(81
0)の形で上記開口部から蒸発する現象を利用するもの
である。この方法によればSol再結晶化層の酸素濃度
を低減化できそれにより結晶欠陥の少ないS01層の形
成が可能である。
Lett, 47 (1985057,
This method utilizes the phenomenon of evaporation from the opening in the form of 0). According to this method, the oxygen concentration in the Sol recrystallized layer can be reduced, thereby making it possible to form an S01 layer with fewer crystal defects.

しかしながらこの方法では保護膜が連続でない本発明は
上記従来の問題点を鑑みてなされたもので、その目的は
、再結晶化過程でのSol中の酸素濃度を低減化し、結
晶欠陥が少なく平坦性に優れた高品質な801層を形成
することである。
However, with this method, the protective film is not continuous.The present invention was made in view of the above-mentioned conventional problems.The purpose of the present invention is to reduce the oxygen concentration in Sol during the recrystallization process, and to achieve flatness with few crystal defects. The objective is to form a high quality 801 layer with excellent properties.

[発明の構成〕 (問題点を解決するための手段) 本発明は上記目的を達成するために絶縁物層を被着した
半導体基板上に半導体結晶層を形成する方法においてこ
の半導体結晶層とすべき半導体層の上部に高融点金属酸
化物膜を被着した後、前2半導体層を溶融・再結晶化し
て半導体結晶層を形成せしめることを特徴とする半導体
結晶層の製造方法を提供する。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for forming a semiconductor crystal layer on a semiconductor substrate on which an insulating layer is deposited. A method for manufacturing a semiconductor crystal layer is provided, which comprises depositing a high-melting point metal oxide film on the top of the semiconductor layer, and then melting and recrystallizing the previous two semiconductor layers to form a semiconductor crystal layer.

(作用) 本発明の原理は、801表面保護膜として酸素原子や酸
化シリコン分子に対し透過性に富む物質、即ち、高融点
金属酸化物膜を用いることにより、例えば電子ビームを
用いたSolの再結晶化過程でSol中の過剰な酸素を
外方拡散つまり、表面から蒸発させ、Sol再結晶化層
の酸素濃度的に除去する目的で前記保護膜上にシリコン
層や金属層を堆積する方法も有効である。
(Function) The principle of the present invention is that by using a material highly permeable to oxygen atoms and silicon oxide molecules, that is, a high melting point metal oxide film, as the 801 surface protective film, Sol can be regenerated using an electron beam, for example. There is also a method of depositing a silicon layer or a metal layer on the protective film for the purpose of outward diffusion of excess oxygen in Sol during the crystallization process, that is, evaporation from the surface, and removing the oxygen concentration of the Sol recrystallized layer. It is valid.

(実施例) 以下、本発明による実施例を図面を用いて説明する。第
1図は、本発明の第1の実施例を示す工程断面図である
。ここで用いられる試料(lO)は、まず第1図(a)
に示すように、方位の単結晶シリコン基板(11)上に
CVD法により厚さ 1.5μmにシリコン酸化(St
 02 )膜(12)を堆積し、その上部全面にシラン
(SI H4)の熱分解を用いたCVD法により厚さ 
0.6μmの多結晶シリコン層(13)を堆積しその上
部にスパッタ法により高融点成はターゲツト材の膜の組
成よりも酸素が減少し、Zr02−xとなるため、スパ
ッタチャンバ中に微により、多結晶シリコン層(13)
を順次、溶融・再結晶化し単結晶シリコン層(13a)
を形成し、801層とした。
(Example) Hereinafter, an example according to the present invention will be described using the drawings. FIG. 1 is a process sectional view showing a first embodiment of the present invention. The sample (lO) used here is first shown in Figure 1(a).
As shown in Figure 2, silicon oxidation (St
02) A film (12) was deposited, and the thickness was
A 0.6 μm polycrystalline silicon layer (13) is deposited on top of it by sputtering to form a high melting point layer, which contains less oxygen than the target material film composition and becomes Zr02-x. , polycrystalline silicon layer (13)
are sequentially melted and recrystallized to form a single crystal silicon layer (13a).
was formed to have 801 layers.

電子ビーム(15)の走査は、T、1lao+asak
l et al、。
The scanning of the electron beam (15) is T, 1lao+asak
l et al.

J、Appl、Phys、59(198B)2971.
 l:よる方法を用いた。
J. Appl. Phys. 59 (198B) 2971.
l: The following method was used.

即ち、36MHzの振幅変調した正弦波により半値幅約
150μmのスポットビームを一方向に高速偏向するこ
とにより、長さ約5 m11に疑似的に線状化したもの
を用い、振幅変調には周波数10k Hzで線状化ビー
ムの長さ方向強度分布を均一化するために計算機制御さ
れた波形をもつ変調波を用いた。
That is, a spot beam with a half-width of about 150 μm is deflected in one direction at high speed using a 36 MHz amplitude-modulated sine wave, and a pseudo-linear beam with a length of about 5 m11 is used. A modulated wave with a computer-controlled waveform was used to equalize the longitudinal intensity distribution of the linearized beam at Hz.

この線状化されたビーム(15)をビーム加速電圧12
kV、ビーム電流9.5mAs走査速度100mm/s
結晶シリコン層(13)の溶融・再結晶化する場合には
、はぼ走査方向を平行に平均間隔10μmの結晶粒界が
多数存在するが、上記実施例では平均間隔が200μm
となり、均一な単結晶領域の面積が飛躍的に増大した。
This linearized beam (15) is heated to a beam acceleration voltage of 12
kV, beam current 9.5mAs scanning speed 100mm/s
When the crystalline silicon layer (13) is melted and recrystallized, there are many crystal grain boundaries parallel to the scanning direction with an average interval of 10 μm, but in the above example, the average interval is 200 μm.
As a result, the area of the uniform single crystal region increased dramatically.

この時、Z「02層(14)と単結晶シリコン層(13
a)の界面ではZr5IOi!l:;Z r O2+ 
SI Q 2の反応が起こり、この界面に極薄い810
2層が形成されてこの界面からZ「02層表面に向かっ
て酸素濃度勾配が高くなっているものと考えられる。
At this time, the Z"02 layer (14) and the single crystal silicon layer (13)
At the interface a), Zr5IOi! l:;Z r O2+
A reaction of SI Q 2 occurs, and an extremely thin 810
It is thought that two layers are formed and the oxygen concentration gradient increases from this interface toward the surface of the Z'02 layer.

次に本発明の第2の実施例について第2図を用いて説明
する。
Next, a second embodiment of the present invention will be described using FIG. 2.

施例と同様に走査型電子ビーム(15)を走査して、多
結晶シリコン層を溶融・再結晶化させることにより30
1層を形成することができる。尚、第1図と同一のもの
は同一の符号を付して示し、その形成方法は第1の実施
例と同様であるので詳細な説明は省略する。
As in the example, the scanning electron beam (15) is scanned to melt and recrystallize the polycrystalline silicon layer.
One layer can be formed. Components that are the same as those in FIG. 1 are denoted by the same reference numerals, and the method of forming them is the same as in the first embodiment, so detailed explanation will be omitted.

この結果得られた801層では先の第1の実施例よりも
結晶粒界の発生はより少なかった。つまり、結晶粒界の
間隔は2〜3 mmであり、部分的には〜5報の間隔の
領域も存在する。この様な大面積の単結晶層が得られる
ことにより、その後この単結晶層に半導体素子を形成す
る上でも有効である。
In the resulting 801 layer, fewer grain boundaries were generated than in the first example. In other words, the interval between grain boundaries is 2 to 3 mm, and there are some regions with an interval of ~5 mm. Obtaining such a large-area single crystal layer is also effective in subsequently forming semiconductor elements on this single crystal layer.

この結果は、再結晶化の過程において前述した過剰な酸
素がZr 02層(14)中を拡散し、このz「02上
に被着された多結晶シリコンIl?IC1B)のシリコ
ン原子と反応して5102層が形成されて、501層中
の酸素濃度がシリコン中の酸素の固溶限よりも大幅に低
いものとなり、結晶粒界発生が位の単結晶シリコン基板
(11)上にCVD法により厚さ2.0amの5I02
膜(12)を堆積し、通常のフォトエツチングにより幅
2.0μmのシード部とすべき部分を除去して開孔部(
17)を形成する。次いでSiH4の熱分解を用いたC
VD法により前記開孔部(17)及び5102膜(12
)上全面に連続して厚さ 0.6μmの多結晶シリコン
層(13)を堆積し、その上部に第2の実施例と、全く
同様にしてZrO2層(14)、多結晶シリコン層(1
6)を順次堆積させたものである。第3図(b)に示す
ようにこの試料上に第1の実施例と同様に走査型電子ビ
ームアニール(15)をA′から矢印方向に走査するこ
とにより、多結晶シリコン層(13)を単結晶シリコン
層(13a)とした。この結果得られた801層はシー
ド部を通じて横方向エピタキシャル成長しているため基
板(11)のシリコンと同一方位の単結晶となっている
。この実施例において結晶粒界の発生はほとんど見られ
ず5市角パターンこのシードで囲まれた領域が結晶粒界
の無い完全な単結晶層が得1″層 ではZr 02層(14)の上部に設ける酸素吸収層の
材料は必ずしも多結晶シリコン層(16)でなくてもよ
く、非晶質シリコン、ゲルマニウム、Ga As 。
This result shows that during the recrystallization process, the above-mentioned excess oxygen diffuses into the Zr02 layer (14) and reacts with the silicon atoms of the polycrystalline silicon Il?IC1B) deposited on this Zr02 layer. The 5102 layer is formed, and the oxygen concentration in the 501 layer is much lower than the solid solubility limit of oxygen in silicon. 5I02 with a thickness of 2.0am
A film (12) is deposited, and a portion with a width of 2.0 μm that should be a seed portion is removed by normal photoetching to form an opening (
17). Then C using pyrolysis of SiH4
The opening part (17) and the 5102 membrane (12
) A polycrystalline silicon layer (13) with a thickness of 0.6 μm is deposited continuously over the entire surface, and a ZrO2 layer (14) and a polycrystalline silicon layer (13) are deposited on top of it in exactly the same manner as in the second embodiment.
6) were deposited sequentially. As shown in FIG. 3(b), a polycrystalline silicon layer (13) is formed on this sample by scanning electron beam annealing (15) from A' in the direction of the arrow in the same manner as in the first embodiment. A single crystal silicon layer (13a) was used. The resulting layer 801 is epitaxially grown in the lateral direction through the seed portion, so that it is a single crystal with the same orientation as the silicon of the substrate (11). In this example, almost no grain boundaries were observed, and the region surrounded by the seeds in the 5-square pattern formed a complete single crystal layer with no grain boundaries. The material of the oxygen absorption layer provided in the layer is not necessarily a polycrystalline silicon layer (16), but may be amorphous silicon, germanium, or GaAs.

Ga P、等の半導体層或いは、Sn、T1.Hf。A semiconductor layer such as Ga, P, etc., or a semiconductor layer such as Sn, T1. Hf.

Nb、Fe、Cu、In、sb、Ni、Pd。Nb, Fe, Cu, In, sb, Ni, Pd.

へ1等の金属層等でも良い。It may also be a metal layer such as 1st grade.

また、上述の第1乃至第3の実施例では、SOlの表面
保護層としてジルコニウム酸化物層を用いたが、ハフニ
ウム酸化物、チタン酸化物、及びそれらにイツトリウム
酸化物とシリコン酸化物を混合したもの等を用いても同
様の効果が得られる。
In addition, in the first to third embodiments described above, a zirconium oxide layer was used as the surface protective layer of SOl, but hafnium oxide, titanium oxide, and mixtures of yttrium oxide and silicon oxide were also used. A similar effect can be obtained by using other materials.

そしてこれらの表面保護層の形成にスパッタ法を用いた
が、真空蒸着法、CVD法等により形成しターやランプ
加熱等を用いたゾーンメルティング法(ZMR)等を用
いても同様な効果が得られる。
Although sputtering was used to form these surface protective layers, the same effect could be obtained by forming them by vacuum evaporation, CVD, etc., and by using zone melting (ZMR), which uses tar or lamp heating, etc. can get.

[発明の効果] 以上、述べてきたように本発明によれば、従来の501
層中の過剰な酸素の析出に起因した結晶欠陥の発生を大
幅に低減することができる。
[Effect of the invention] As described above, according to the present invention, the conventional 501
The occurrence of crystal defects caused by excessive precipitation of oxygen in the layer can be significantly reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明による実施例を示す断面図、
第4図及び第5図は従来例を説明するための説明図であ
る。 11・・・・・・基板、 12・・・・・・酸化膜、 13・・・・・・多結晶シリコン膜、 13a・・・・・・単結晶シリコン層、14・・・・・
・高融点金属酸化物層、15・・・・・・エネルギービ
ーム、 16・・・・・・多結晶シリコン層。 出願人 工業技術院長 飯塚幸三 第1図 第2図 第3図 I 第4図
1 to 3 are cross-sectional views showing embodiments of the present invention,
FIGS. 4 and 5 are explanatory diagrams for explaining a conventional example. 11...Substrate, 12...Oxide film, 13...Polycrystalline silicon film, 13a...Single crystal silicon layer, 14...
- High melting point metal oxide layer, 15... Energy beam, 16... Polycrystalline silicon layer. Applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka Figure 1 Figure 2 Figure 3 Figure I Figure 4

Claims (6)

【特許請求の範囲】[Claims] (1)絶縁物層を被着した半導体基板上に半導体結晶層
を形成する方法において、この半導体結晶層とすべき半
導体層の上部に高融点金属酸化物膜を被着した後、前記
半導体層を溶融・再結晶化して半導体結晶層を形成せし
めることを特徴とする半導体結晶層の製造方法。
(1) In a method of forming a semiconductor crystal layer on a semiconductor substrate on which an insulating layer is deposited, a high melting point metal oxide film is deposited on the top of the semiconductor layer to be used as the semiconductor crystal layer, and then the semiconductor layer is 1. A method for producing a semiconductor crystal layer, which comprises melting and recrystallizing to form a semiconductor crystal layer.
(2)前記高融点金属酸化物としてジルコニウム系酸化
物、ハフニウム系酸化物、チタン系酸化物、あるいはそ
れらの混合物を用いたことを特徴とする特許請求の範囲
第1項記載の半導体結晶層の製造方法。
(2) The semiconductor crystal layer according to claim 1, wherein a zirconium-based oxide, a hafnium-based oxide, a titanium-based oxide, or a mixture thereof is used as the high-melting point metal oxide. Production method.
(3)前記高融点金属酸化物層の上層に半導体層と金属
層の少なくとも一層が被着されていることを特徴とする
特許請求の範囲第1項記載の半導体結晶層の製造方法。
(3) The method for manufacturing a semiconductor crystal layer according to claim 1, wherein at least one of a semiconductor layer and a metal layer is deposited on the high melting point metal oxide layer.
(4)前記半導体層の再結晶化はエネルギービームの走
査によって前記絶縁物層に設けられた開孔部を介して行
なわれることを特徴とする特許請求の範囲第1項記載の
半導体結晶層の製造方法。
(4) The semiconductor crystal layer according to claim 1, wherein the recrystallization of the semiconductor layer is performed through an opening provided in the insulating layer by scanning an energy beam. Production method.
(5)前記半導体結晶層は半導体単結晶層である特許請
求の範囲第1項記載の半導体結晶層の製造方法。
(5) The method for manufacturing a semiconductor crystal layer according to claim 1, wherein the semiconductor crystal layer is a semiconductor single crystal layer.
(6)前記半導体結晶層とすべき半導体層は、多結晶あ
るいは非晶質半導体層である特許請求の範囲第1項記載
の半導体結晶層の製造方法。
(6) The method for manufacturing a semiconductor crystal layer according to claim 1, wherein the semiconductor layer to be the semiconductor crystal layer is a polycrystalline or amorphous semiconductor layer.
JP22718586A 1986-09-27 1986-09-27 Manufacture of semiconductor crystal layer Granted JPS6384013A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22718586A JPS6384013A (en) 1986-09-27 1986-09-27 Manufacture of semiconductor crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22718586A JPS6384013A (en) 1986-09-27 1986-09-27 Manufacture of semiconductor crystal layer

Publications (2)

Publication Number Publication Date
JPS6384013A true JPS6384013A (en) 1988-04-14
JPH0525384B2 JPH0525384B2 (en) 1993-04-12

Family

ID=16856820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22718586A Granted JPS6384013A (en) 1986-09-27 1986-09-27 Manufacture of semiconductor crystal layer

Country Status (1)

Country Link
JP (1) JPS6384013A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010166035A (en) * 2008-12-15 2010-07-29 Semiconductor Energy Lab Co Ltd Method of manufacturing soi substrate, and method of manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5659694A (en) * 1979-10-18 1981-05-23 Agency Of Ind Science & Technol Manufacture of thin film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5659694A (en) * 1979-10-18 1981-05-23 Agency Of Ind Science & Technol Manufacture of thin film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010166035A (en) * 2008-12-15 2010-07-29 Semiconductor Energy Lab Co Ltd Method of manufacturing soi substrate, and method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH0525384B2 (en) 1993-04-12

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