JPS6376479A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the problems of silicide film peeling-off and of degraded voltage-withstanding capability in a mask oxidation process for the construction of a semiconductor device high in reliability by a method wherein a silicide film is deposited, an amorphous silicon film or polycrystalline silicon film is deposited, and then etching is accomplished for the formation of a gate electrode. CONSTITUTION:A field oxide film 1 and gate oxide film 3 are formed on a semiconductor substrate 2, and a silicide film 4 is deposited on the field oxide film 1 and gate oxide film 3. Next, an amorphous silicon film 8 or polycrystalline silicon film 8 is formed and a gate electrode is constructed by etching, in that order. A mask oxide film 5 is formed in a mask oxidation process to surround the gate electrode, and then a source region 6 and drain region 7 are formed on the semiconductor substrate 2. In this design, possibility is low of the silicide film's being oxidized in the mask oxidation process. This in turn prevents the silicide film from peeling off the gate oxide film and the reduction in stress exerted on the gate oxide film results in a reduction in gate voltage-withstanding capability degradation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to polycide dart and silicide dart structures in semiconductor integrated circuits.

[Conventional technology]

A conventional method for manufacturing a semiconductor device having a silicide gate is shown in FIGS. 2(a) to 2(d). First, Figure 2 (
&), a semiconductor substrate 2 is used, and this semiconductor substrate 2. A field oxide film 1 is formed thereon by field oxidation to form an active region and a field region.

Thereafter, an f-) oxide film 3 made of 5iOt or the like is formed. The thickness of the field oxide film 1 at this time is 400 mm.
0~toooo^, the thickness of the gate oxide film 3 is 50~10
00λ. Next, as shown in FIG. 2, a silicide film 4 is formed on the field oxide film 1 and the gate oxide film 3.
500λ~50 by LPGVD or snow ivy
00^ Deposit. Next, as shown in FIG. 2(c), the f-to-oxide film 3 and the silicide film 4 are etched.
Form a silicate gate electrode. Next, as shown in FIG. 2(d), mask oxidation is performed to form a mask oxide film 5 around the P-to electrode, and then a source region 6 and a drain region 7 are formed by a method such as implantation.

[Problem that the invention seeks to solve]

However, in the conventional method described above, the silicide film 4 is peeled off from the gate oxide film 3 due to mask oxidation, or
Alternatively, even if the silicide film 4 is not peeled off, oxidation of the silicide film 4 causes stress on the silicate oxide 1113, causing a problem that the withstand voltage of the gate oxide film 3 deteriorates. Such a problem would not occur if mask oxidation was not performed, but in this case, charge-up would occur during the in-grain process for forming the source region 6 and drain region 7. '−
) Destruction occurs.

This invention relates to the peeling off of the silicide film in the mask oxidation process as described above. -) It is an object of the present invention to provide a method for manufacturing a semiconductor device with low reliability by eliminating the problem of breakdown voltage deterioration of an oxide film.

[Means for solving problems]

This invention relates to a method for manufacturing a semiconductor device, in which a gate electrode is formed by etching after depositing an amorphous silicon film or a polysilicon film after depositing a silicide film, or by forming an amorphous silicon film or a polysilicon film after forming a P-type electrode. After that, mask oxidation is performed to form a source region and a drain region.

[Effect]

In this invention, a field oxide film and a gate oxide film are formed on a semiconductor substrate, a silicide film is formed on these, and after that, an amorphous silicon film or a polysilicon film is formed on the silicide film to form a gate oxide film. After forming the electrode or forming the r-meter electrode, an amorphous silicon film or the like is deposited, and then a mask oxidation process is performed.In this process, even if the amorphous silicon film is oxidized, the silicide I[ is protected by an amorphous silicon film or the like, and oxidation hardly occurs.

Ninth, peeling of the silicide film is less likely to occur, and stress is less likely to occur in the gate oxide film, making it less likely that the breakdown voltage of the gate oxide film will deteriorate.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, first, as shown in FIG. 2(a), a field oxide film 1 is formed on a semiconductor substrate 2, and then an r-) oxide film 3 is formed. Next, as shown in Figure 2(b),
A silicide film 4 is deposited on field oxide film 1 and gate oxide film 3.

Everything up to this point is the same as before. Next, as shown in FIG.
is deposited by sputtering. At this time, the temperature of the substrate 2 is 25° C. to 400° C., and the sputtering time is 5 seconds to 50 seconds. After that, Figure 1 (
Etching is performed as shown in b) to form dart electrodes. Etching is done by dry etching. The etching gas used was a mixture of SFe, CtCI, Fs, c/l), and the flow rate was t'18 Fa, Fs c/l), and the flow rate was t'18 Fa, Fs, c/l)
.

c, CI F, is 20 cc/Bea. Also, the gas pressure was 200 torr.

Etching time is 90 seconds. Note that the above etching conditions are for the case where the thickness of the silicide film 4 is 2000λ and the thickness of the amorphous silicon film 8 is 700λ. next,
As shown in FIG. 1(c), a mask oxide film 5 is formed around the r-) electrode by mask oxidation. Mask oxidation is
At a temperature of 950℃ in an oxygen atmosphere? ) I went 100m1n. Next, a source region 6 and a drain region 7 are formed in the semiconductor substrate 2 by an implantation process. In this ingla process, the dose is 10"3-" at 40@V.
Enter As.

Here, the gate length and the thickness TI of the silicide film 4.

The thickness T3 of the amorphous silicon film 8 and the oxidation time t of the mask oxidation are important parameters for not causing breakdown voltage deterioration (see FIG. 3(b)).

That is, since the amorphous silicon film 8 can be easily oxidized in an oxidizing atmosphere, in order to prevent the amorphous silicon film 8 from being completely oxidized and the silicide film 4 also being oxidized, it is necessary to The relationship between the thickness T of the amorphous silicon 1118 and the oxidation time t is important, and the film thickness t''p(
t), it is necessary that p (t)≦T, and 'r
+>p(t) is required. Furthermore, from the experimental results that the peeling of the silicide film 4 and the stress on the r-) oxide film 3 become significant depending on the exposed area of the silicide film 4 during mask oxidation, is not protected by the amorphous silicon film 8, the condition L>4T is required. If these conditions are satisfied, the silicide film 4 will not be easily oxidized and deterioration in breakdown voltage will not occur.

Next, a second embodiment of the invention will be described. In this example, the following steps are first performed as shown in FIGS. 2(a) to 2(c). After forming a dart electrode by dry etching as shown in FIG. 2(c), the steps shown in FIG. 3(a) are performed. An amorphous silicon film 8 is deposited around the P-meter electrode as shown. Next, as shown in FIG. 3(b), mask oxidation is performed to form a mask oxide film 5, and then a north region and a drain region are formed by an in-grain process. In this example as well, T,=P(t) is required, and the first
The same effect as in the embodiment is achieved.

FIG. 4 shows dirt pressure resistance data according to an embodiment of the present invention. Three samples are shown in the figure. In this case, an amorphous silicon film 8 of 700λ was deposited.

The thickness of the silicide film 4 was 2000, and the mask oxidation was performed for 100 minutes in an oxygen atmosphere.

In addition, Fig. 5 shows the breakdown voltage characteristics (r-) according to the conventional method, A, B, and C show three samples, the thickness of the silicide film 4 is 2000λ, and the mask oxidation is performed for 100 minutes in an oxygen atmosphere. . Comparing FIG. 4 and FIG. 5, in the present invention, the dielectric breakdown voltage is 30 V, and since no electron traps are generated, gate film deterioration due to mask oxidation does not occur. In contrast, conventionally, the dielectric breakdown voltage is 30
It is lower than V, and electron drag also occurs.

Although the amorphous silicon film 8 is used in each of the above embodiments, the same effect can be achieved even if a polysilicon film is used instead. In this case, the polysilicon film is formed by LPCVD.

〔Effect of the invention〕

As described above, according to the present invention, the mask oxidation process is performed after depositing the amorphous silicon film or polysilicon film on the silicide film forming the gate electrode, so that the silicide film is replaced with the amorphous silicon film in this process. Alternatively, it is protected by a polysilicon film and is less likely to be oxidized. Therefore, peeling of the silicide film from the gate oxide film is prevented, stress on the gate oxide film is reduced, and gate breakdown voltage deterioration is alleviated. Furthermore, since the amorphous silicon film or polysilicon film also functions as a mask for the in-grain process, damage to the gate in the in-grain process can be reduced. Note that when the gate has a polycide structure, even if there is an oxide film on the polysilicon film, peeling of the silicide film can be prevented by using this manufacturing method.

[Brief explanation of the drawing]

Figures 1 (a) to (c) are cross-sectional views of the process according to the first embodiment of the method of this invention, Figures 2 (&) to (d) are cross-sectional views of the process according to the conventional method, and Figure 3 (IL). (b) is a process sectional view according to a second embodiment of the method of the present invention, FIG. 4 is a diagram showing r-) withstand voltage characteristics according to the method of the present invention, and FIG. 5 is a diagram showing gate withstand voltage characteristics according to the conventional method. DESCRIPTION OF SYMBOLS 1... Field oxide film, 2... Semiconductor substrate, 3...
... Dirt oxide film, 4... Silicide film, 5... Mask oxide film, 6... Source region, 7... Drain region, 8... Amorphous silicon film. Mokuen B Ha no To 1 Furukihiide 11; Slander 1 company b car surface map Figure 1 Ordinance issued 11M@＞1 Shōgata Idel+: Juru Komusei 101 Surface map Figure 1 4 Series 11 h lol 5 ・Mass 7 acid i V sacrifice 6' north no I-knee (1 doshiin @ 珘8 ajl reference silicon to Akiragi X method 1-J
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Claims (1)

[Claims] (1) (a) A step of forming a field oxide film and a gate oxide film on the semiconductor substrate, (b) A step of depositing a silicide film on the field oxide film and the gate oxide film, and (c) A step of depositing a silicide film on the silicide film. (d) forming a mask oxide film around the gate electrode by mask oxidation (e) A method for manufacturing a semiconductor device, comprising the step of forming a source region and a drain region on a semiconductor substrate.