JPS6353978A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve an erasure characteristic and to reduce an effect due to the nonuniformity in a film thickness, by using a CVD method when an insulating layer is formed on an erase gate, and by forming this insulating layer so that it has a large film thickness. CONSTITUTION:A field oxide film 12 is formed on the surface of a substrate, and further a polycrystalline Si layer is formed by deposition. Next, the polycrystalline Si layer is doped with an impurity and thereafter removed selectively so as to form an erase gate 18. Then, an insulating layer 13 is formed, and thereafter only an oxide film on the gate 18 is removed selectively. Next, an insulating layer 20 is formed on the gate 18 by using a CVD method. There after a polycrystalline Si layer is formed by deposition on the whole surface of the base by using the CVD method. Then, a floating gate 16 is formed in this polycrystalline Si layer. Thereafter, an insulating layer 14 is formed, Then, a polycrystalline Si layer is deposited on the base, and an impurity is doped to form a control gate 17.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor memory device, and particularly relates to a method of manufacturing a semiconductor memory device, and in particular to an EEP device that can be electrically erased and written.
It is used for manufacturing ROM.

(Prior Art) Conventionally, a nonvolatile semiconductor memory device capable of electrically erasing and writing data has been configured as shown in FIG. 4, for example. In FIG. 4, 11 is a semiconductor substrate, 12 is a field oxide film, 13, 14 and 15 are insulating layers formed by thermal oxidation, 16 is a first gate (floating gate), and 17 is a second gate ( Control gate i-), 18 is a third gate (erase gate). This structure includes an isolated Ii layer 13, a floating gate 16.
The EPROM structure consisting of the insulating layer 14 and the control gate 17 is insulated! IIJ15 and erase gate 18
By adding , electrical erasing is possible. Note that in FIG. 4, the source and drain regions formed in the semiconductor substrate 11 are omitted, and the formation of the source and drain regions will not be particularly explained in the following description as it is known.

Such a nonvolatile semiconductor memory device is shown in FIGS.
It is formed through the steps shown in (C). First, (a
) As shown in the figure, a semiconductor substrate 11 is selectively oxidized by exposing it to a high-temperature oxidizing atmosphere using an oxidation-resistant film as a mask to form a thick oxide film (field oxide film) 12 on the surface. A polycrystalline silicon layer is deposited over the entire surface using phase epitaxy (CVD). Next, after the polycrystalline silicon layer is doped with impurities by diffusion or the like, photoetching is performed to selectively remove the polycrystalline silicon layer to form an erase gate 18.

Next, as shown in FIG. 3B, thermal oxidation is performed to form a first insulating layer 13 with a thickness of 300 to 700 layers on the semiconductor substrate.
form. At this time, the insulating layer 1 on the erase gate 18
3 is approximately 1.5 times as thick as that of the semiconductor substrate 11,
Photoetching is performed using the photoresist 19 as a mask to selectively remove only the oxide film on the erase gate 18. Note that although the diagram (b) shows the case where only the insulating layer 13 interposed between the floating gate 16 and the erase gate 18, which is related to the erase characteristics, is removed, it is possible to remove all the insulating layer 13 on the erase gate 18. May be removed.

Next, thermal oxidation is performed to form an insulating layer 15 with a thickness of 200 to 500 layers on the erase gate 18 as shown in FIG. do. After this polycrystalline silicon layer is doped with impurities by diffusion or the like, it is patterned by photoetching to form a floating gate 16. Thereafter, thermal oxidation is performed to form an insulating layer 14 having a thickness of 200 to 700 layers on the semiconductor substrate.

Thereafter, a polycrystalline silicon layer is deposited on the semiconductor substrate using the CVD method, doped with impurities by diffusion, etc., and then photoetched and patterned to form the control gate 17, as shown in FIG. The configuration will be as shown.

By the way, conventionally, as described above, the resist #1115 on the erase gate 18 is formed by thermal oxidation, but in order to obtain good YI quality and good erase characteristics, it is necessary to reduce the film thickness. This requires special techniques such as dilute oxidation. Moreover, it is difficult to control the film thickness when forming a thermal oxide film, which tends to cause variations from cell to cell, and increases erasing time. Moreover, in the worst case, there is a problem that the data cannot be erased.

FIG. 6 shows the erase characteristics of a semiconductor memory device formed by the manufacturing method described above. As shown in the figure, there are large variations in erasing characteristics, and erasing may take several seconds or may not be possible.

(Problems to be Solved by the Invention) As mentioned above, in the conventional manufacturing method of semiconductor memory devices, variations in erase characteristics are likely to occur, special oxidation technology is required, and control of film thickness is difficult. There are drawbacks.

This invention was made in view of the above-mentioned circumstances, and its purpose is to reduce variations in erase characteristics, obtain a good insulating film without using special oxidation technology, and improve film quality. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device whose thickness can be easily controlled.

[Structure of the Invention] (Means and Effects for Solving the Problem) In order to achieve the above object, the present invention uses the CVD method when forming an insulating layer on the erase gate, and I8
The edge layer is formed thickly. This is intended to improve the erasing characteristics and to reduce the influence of variations in film thickness.

(Example) Hereinafter, an actual example of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(d) show the manufacturing steps of the semiconductor memory device of the present invention in the order of the steps. In FIG. 1, the same components as in FIG. 4 or 5 are designated by the same reference numerals. It is attached.

First, as shown in FIG.
Form field oxide [112] on the surface. A polycrystalline silicon layer is deposited over the entire surface of this semiconductor substrate using chemical vapor deposition (CVD). Next, after the polycrystalline silicon layer is doped with impurities by diffusion or the like, photoetching is performed to selectively remove the polycrystalline silicon layer to form an erase gate 18.

Next, as shown in FIG. 3B, thermal oxidation is performed to form a first insulating layer 13 with a thickness of 300 to 700 layers on the semiconductor substrate.
form. Thereafter, photoetching is performed using the photoresist 19 as a mask to selectively remove only the oxide pattern on the erase gate 18.

At this time, the insulating layer 13 on the erase gate 18 may be completely removed, or the floating gate 13 may be completely removed as shown in FIG.
6 and the erase gate 18
You may selectively remove only that.

Next, as shown in Figure (C), an insulating layer (second insulating layer) 20 having a thickness of 500 to 2,000 layers is formed on the erase gate 18 using the CVD method, and photoetching is performed. pattern. Thereafter, a polycrystalline silicon layer is deposited over the entire surface of the semiconductor substrate using the CVD method. After this polycrystalline silicon layer is doped with impurities by diffusion or the like, it is patterned by photoetching to form a floating gate 16. Thereafter, thermal oxidation is performed to form a layer on the semiconductor substrate with a thickness of 200 to 70 mm.
An insulating layer (third insulating layer) 14 of 0.00 people is formed.

Thereafter, as shown in Figure (d), a polycrystalline silicon layer is deposited on the semiconductor substrate 1 using the CVD method, doped with impurities by diffusion, etc., and patterned by photoetching. A control gate 17 is formed.

According to this manufacturing method, since the CVD method is used to form the insulating layer 20 on the erase gate 18, the film thickness can be easily controlled, and the film thickness can be formed thicker than in the case of thermal oxidation. Accordingly, variations in erasing characteristics due to variations in film thickness can be reduced.

Moreover, there is no need to use special oxidation techniques such as diluted oxidation or special manufacturing equipment, and a conventionally used CVD equipment can be used.

FIG. 2 shows the erase characteristics of the semiconductor memory device formed by the manufacturing method shown in FIG. 1 above. As shown,
Erasing time can be accelerated to several tens of milliseconds to several seconds.
Furthermore, the number of bits that cannot be erased can be significantly reduced.

FIG. 3 is for explaining another embodiment of the present invention. In the process shown in FIG. After forming this insulation [20
The insulating layer 21 of ~5.00 layers was formed by thermal oxidation. In the subsequent steps, the floating gate 1G, the insulating layer 14, and the control gate 17 are sequentially formed in the same manner as in FIGS. 1(c) and 1(d).

Even in such a manufacturing method, the same effects as in the above-mentioned embodiments can be obtained.

[Effects of the Invention] As explained above, according to the present invention, variations in erase characteristics can be reduced, a good insulating film can be obtained without special oxidation technology, and the film thickness can be easily controlled. A method for manufacturing the device is obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows the erase characteristics of a semiconductor memory device formed using the manufacturing method shown in FIG. 1 above. 30 is a diagram for explaining another embodiment of the present invention, FIG. 4 is a diagram showing the configuration of a conventional semiconductor memory device, and FIG. 5 is a diagram for explaining a conventional method for manufacturing a semiconductor memory device. FIG. 6 is a diagram showing the erase characteristics of a semiconductor memory device formed using the manufacturing method shown in FIG. 5. 11... Semiconductor substrate, 12... Field fermentation film,
13...First insulating layer, 14...Third insulating layer, 1
6... Floating gate, 17... Control gate, 18... Erasing gate, 20... Second insulating layer, 21... Fourth insulating layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 30 Figure 4

Claims (2)

[Claims] (1) selectively forming a field oxide film on the semiconductor substrate; and forming a first insulating layer on the semiconductor substrate in an element region surrounded by the field oxide film;
forming an erase gate on the field oxide film; forming a second insulating layer on the erase gate by chemical vapor deposition; and forming a floating gate on the first insulating layer. A method for manufacturing a semiconductor memory device, comprising the steps of: forming a third insulating layer on the floating gate; and forming a control gate on the third insulating layer. (2) The step of forming the second insulating layer further comprises the step of forming a fourth insulating layer by thermal oxidation on the second insulating layer. A method for manufacturing a semiconductor memory device according to section 1.