KR19990005893A - Spacer Formation Method of Semiconductor Device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a stacked gate spacer in a flash memory device having a split gate structure.

2. Technical problem to be solved by the invention

When forming a split gate of a flash memory device, an under cut phenomenon occurs in a process of forming an spacer by etching an oxide film and a nitride film on the stacked gate structure and etching the same.

3. Summary of the Solution of the Invention

Oxide layer is deposited and then etched to form oxide spacers first, and nitride layer is deposited and etched again to form spacers to minimize the exposed portion of the oxide layer, thereby suppressing undercut phenomenon occurring in subsequent select gate formation processes. box.

Description

Spacer Formation Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a stacked gate spacer of a flash memory device using a split gate.

1 (a) and 1 (b) are cross-sectional views sequentially shown to explain a method of forming a spacer of a conventional semiconductor device.

In the flash memory device fabrication process, as shown in FIG. 1A, the tunnel oxide film 12, the first polysilicon layer 13 for the floating gate, the dielectric film 14, and the control gate material are selected in the selected region on the silicon substrate 11. The polysilicon layer 15 is sequentially deposited to form a stacked gate.

In forming the spacer on the side of the laminated structure gate as described above, the spacer was formed by etching and forming an oxide film through an oxidation process of the polysilicon layer. However, since the oxide film formation rate is changed due to the impurity concentration difference between the first polysilicon layer 13 and the second polysilicon layer 15 in the manufacturing process, the first polysilicon layer 13 and the second polysilicon layer 15 are Deformed to act as a factor to reduce the characteristics of the device. Therefore, at present, by depositing an HTO (High Temperature Oxide) 16 film rather than forming an oxide film through an oxidation process, an oxide film having a uniform thickness may be obtained without changing the stacked structure gate.

On the other hand, since the undercut phenomenon occurs at the lower portion due to the exposure of the oxide film during the subsequent select gate forming process, a nitride layer 17 is deposited on the HTO layer 16 and spacers are formed by etching.

However, as shown in FIG. 1B, due to the thickness of the HTO film 16 deposited on the silicon substrate 11, the HTO film 16 under the nitride film 17 after spacer etching is exposed as A. FIG. Therefore, there is still a high probability of undercut phenomenon.

Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of suppressing undercut generation elements as much as possible to improve the reliability of the device.

The present invention for achieving the above object is a step of sequentially depositing a tunnel oxide film, a floating gate layer, a dielectric film, a control gate layer in a selected region on the semiconductor substrate to form a stacked structure gate, and comprising the stacked structure gate Depositing an oxide film with a uniform thickness on the entire structure, etching the oxide film to remain at a predetermined thickness, and depositing and etching a nitride film on the oxide film to form a spacer.

1 (a) and 1 (b) are cross-sectional views sequentially shown to explain a method of forming a spacer of a conventional semiconductor device.

2 (a) to 2 (d) are cross-sectional views sequentially shown to explain the method for forming a spacer according to the present invention.

Explanation of symbols for the main parts of the drawings

11 and 21: silicon substrate 12 and 22: tunnel oxide film

13 and 23: first polysilicon layer 14 and 24: dielectric film

15 and 25: second polysilicon layer 16 and 26: HTO (High Temperature Oxide) film

17 and 27: nitride film

The present invention will be described in detail with reference to the accompanying drawings.

2 (a) to 2 (d) are cross-sectional views sequentially shown to explain the method for forming a spacer according to the present invention.

FIG. 2A shows the tunnel oxide film 22, the first polysilicon layer 23 for the floating gate, the dielectric film 24, and the second polysilicon layer 25 for the control gate in the selected region on the silicon substrate 21. FIG. After depositing sequentially to form a laminated structure gate, it is sectional drawing which deposited the HTO film | membrane 26 in the uniform thickness of about 200 GPa-400 GPa on the whole structure containing a laminated structure gate.

As shown in FIG. 2B, the HTO film 26 is etched to form a spacer. At this time, the etching process is performed by precisely controlling the HTO film 26 to remain at a thickness of about 50 GPa to 150 GPa on the silicon substrate 21.

FIG. 2C is a cross-sectional view of a nitride film 27 deposited at a thickness of 200 GPa to 500 GPa on top of a structure in which a spacer is formed of an HTO film 26.

As shown in FIG. 2 (d), the nitride layer is etched through the second etching process to form a complete spacer.

Therefore, by depositing an oxide film and then etching to form a spacer and then depositing a nitride film thereon to form a spacer by a second etching process, the oxide film exposed to the lower portion of the nitride film is minimized, so that the subsequent select gate forming process Undercut behavior can be suppressed.

As described above, according to the present invention, the leakage current of the flash memory device due to the undercut phenomenon can be eliminated, thereby improving the data storage and program characteristics of the device.

Claims (6)

Sequentially depositing a tunnel oxide film, a floating gate layer, a dielectric film, and a control gate layer in a selected region on the semiconductor substrate to form a stacked gate, and depositing an oxide film with a uniform thickness over the entire structure including the stacked gate. Depositing and etching the oxide film to remain at a predetermined thickness, and depositing and etching a nitride film on the oxide film to form a spacer. The method of claim 1, wherein the oxide film is deposited using any one of HTO, MTO, and TEOS. The method of claim 1, wherein the oxide film is deposited to a thickness of 200 kPa to 400 kPa. 2. The method of claim 1, wherein the oxide film is controlled to be etched so as to remain on a semiconductor substrate with a thin thickness of 50 GPa to 150 GPa. The method of claim 1, wherein the nitride film is deposited to a thickness of 200 GPa to 500 GPa. The method of claim 1, wherein the floating gate layer and the control gate layer use polysilicon.