KR20000001682A - Method of forming eprom cell - Google Patents
Method of forming eprom cell Download PDFInfo
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- KR20000001682A KR20000001682A KR1019980022052A KR19980022052A KR20000001682A KR 20000001682 A KR20000001682 A KR 20000001682A KR 1019980022052 A KR1019980022052 A KR 1019980022052A KR 19980022052 A KR19980022052 A KR 19980022052A KR 20000001682 A KR20000001682 A KR 20000001682A
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- oxide film
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- floating gate
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 비휘발성 반도체 소자 제조방법에 관한 것으로, 보다 상세하게는 이피롬(이하, EPROM이라 한다) 셀을 이루는 ONO 구조의 절연막 형성 공정 변경을 통하여 EPROM 셀 구동시 야기되는 차지 로스(charge loss) 불량을 줄일 수 있도록 한 EPROM 셀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor device, and more particularly, to a charge loss caused when driving an EPROM cell through a process of changing an insulating film forming process of an ONO structure that forms an epipyrom (hereinafter referred to as EPROM) cell. The present invention relates to an EPROM cell formation method capable of reducing defects.
종래 일반적으로 이용되어 오던 EPROM 셀은 도 1에 제시된 단면도에서 알 수 있듯이, ONO(제 1 산화막/질화막/제 2 산화막) 구조의 절연막(20)을 사이에 두고, 그 상·하부에 폴리실리콘 재질의 플로팅 게이트(10)와 폴리사이드 재질의 컨트롤 게이트(30)가 적층되도록 이루어져, 상기 절연막(20)은 통상 CHE(channel hot electron injection) 방식에 의해 그 내부에 차지(charge)를 저장하도록 하고 있다.The conventionally used EPROM cell has a polysilicon material on and under the insulating film 20 of the ONO (first oxide film / nitride film / second oxide film) structure, as shown in the cross-sectional view shown in FIG. The floating gate 10 and the control gate 30 made of polyside are stacked so that the insulating film 20 stores charge therein by a channel hot electron injection (CHE) method. .
따라서, 상기 구조의 EPROM 셀은 도 2의 공정 블록도에서 알 수 있듯이 다음의 제 3 단계를 거쳐 제조된다.Therefore, the EPROM cell of the above structure is manufactured through the following third step as can be seen in the process block diagram of FIG.
제 1 단계(100)로서, 반도체 기판 상에 폴리실리콘 재질의 제 1 도전성막을 형성하고, 상기 기판 표면이 소정 부분 노출되도록 이를 선택식각하여 플로팅 게이트(10)를 형성한다.In a first step 100, a first conductive film made of polysilicon is formed on a semiconductor substrate, and the substrate is selectively etched to expose a predetermined portion of the surface of the substrate to form a floating gate 10.
제 2 단계(102)로서, 상기 플로팅 게이트(10)를 포함한 상기 기판 상에 80 ~ 90Å의 두께의 제 1 산화막(20a)과 120 ~ 140Å의 두께의 질화막(20b) 및 40 ~ 50Å의 두께의 제 2 산화막(20c)으로 이루어진 절연막(20)을 형성한다. 이때, 제 1 산화막(20a)은 850℃의 온도에서 산화 공정을 거쳐 형성되고, 질화막(20b)은 CVD법을 이용하여 형성되며, 제 2 산화막(20c)은 950℃의 온도에서 산화 공정을 거쳐 형성된다.As a second step 102, a first oxide film 20a having a thickness of 80 to 90 GPa and a nitride film 20b having a thickness of 120 to 140 GPa and a thickness of 40 to 50 GPa are formed on the substrate including the floating gate 10. An insulating film 20 made of the second oxide film 20c is formed. In this case, the first oxide film 20a is formed through an oxidation process at a temperature of 850 ° C, the nitride film 20b is formed using a CVD method, and the second oxide film 20c is subjected to an oxidation process at a temperature of 950 ° C. Is formed.
이와 같이 제 2 산화막(20c)을 제 1 산화막(20a)보다 높은 온도에서 성장시킴에도 불구하고 제 1 산화막(20a)과 제 2 산화막(20b) 간에 두께 차이가 심하게 발생되는 것은, 제 1 산화막(20a)의 경우는 하지막이 불순물이 도핑된 폴리실리콘 재질의 플로팅 게이트(10)인 관계로 인해 산화막 성장이 빨리 이루어지는 반면, 제 2 산화막(20c)의 경우는 하지막이 질화막인 관계로 인해 전자의 경우보다 산화막 성장이 더디게 이루어지기 때문이다.As described above, despite the growth of the second oxide film 20c at a higher temperature than the first oxide film 20a, a significant difference in thickness between the first oxide film 20a and the second oxide film 20b occurs. In the case of 20a), the oxide film grows rapidly due to the relationship between the underlying film and the floating gate 10 made of polysilicon doped with impurities, whereas the second oxide film 20c exhibits the nitride film due to the relationship between the underlying film and the nitride film. This is because oxide film growth is slower.
따라서, 제 1 산화막(20a)과 제 2 산화막(20c)의 두께를 서로 동일하게 가져가기 위해서는 제 1 산화막(20a) 성장시 기존보다 낮은 온도(예컨대, 850℃ 이하의 온도)에서 산화 공정을 실시하던가 혹은 제 2 절연막(20c) 성장시 기존보다 높은 온도(예컨대, 950℃ 이상의 온도)에서 산화 공정을 실시해 주어야 한다.Therefore, in order to have the same thicknesses of the first oxide film 20a and the second oxide film 20c, the oxidation process is performed at a lower temperature than the conventional one (for example, a temperature of 850 ° C. or less) when the first oxide film 20a is grown. When the second insulating film 20c is grown or oxidized, the oxidation process should be performed at a higher temperature than the conventional temperature (eg, 950 ° C. or higher).
그러나, 전자의 방법을 적용하여 막질을 성장시킬 경우에는 제 1 산화막(20a) 자체의 두께를 낮게 가져갈 수는 있으나, 저온 공정으로 인해 제 1 산화막(20a)의 막질 저하가 우려되므로 실 공정 적용에 어려움이 따르게 되고, 반면 후자의 방법을 적용하여 막질을 성장시킬 경우에는 서멀 버짓(thermal budget) 및 질화막(20b)의 산화가 유발되므로 그 적용에 어려움이 따르게 되어, 현재는 실 공정에 적용하지 못하고 있는 실정이다.However, when the film quality is grown by applying the former method, although the thickness of the first oxide film 20a itself can be kept low, the film quality of the first oxide film 20a may be lowered due to the low temperature process. On the other hand, when the film quality is grown by applying the latter method, the thermal budget and the oxidation of the nitride film 20b are caused, so that the application is difficult, and the present method cannot be applied to the actual process. There is a situation.
제 3 단계(104)로서, 상기 절연막(20) 상에 폴리사이드 재질의 제 2 도전성막을 형성하고, 상기 플로팅 게이트(10) 양 에지측 상의 상기 절연막(20) 표면이 소정 부분 노출되도록 이를 선택식각하여 컨트롤 게이트(30)를 형성하므로써, 본 공정 진행을 완료한다.As a third step 104, a second conductive film of polyside material is formed on the insulating film 20, and the etching is performed so that a predetermined portion of the surface of the insulating film 20 on both edges of the floating gate 10 is exposed. By forming the control gate 30, the process progress is completed.
그러나, 상기 공정을 적용하여 EPROM 셀을 형성할 경우에는 기 언급된 사유로 인해 절연막(20)을 이루는 제 1 산화막(20a)과 제 2 산화막(20b)의 두께를 동일하게 가져갈 수 없으므로, EPROM 셀 구동시 컨트롤 게이트에 고전압이 인가되게 되면, 그 두께 차이로 인해 플로팅 게이트(10) 내에 채워진 전자의 일부가 컨트롤 게이트(30)쪽으로 빠져 나가는 일명, 차지 로스 현상이 발생하게 된다. 이러한 현상이 발생될 경우, EPROM 셀의 전체적인 동작 특성이 저하되는 불량이 초래되므로, 이에 대한 개선책이 시급하게 요구되고 있다.However, in the case of forming the EPROM cell by applying the above process, since the thicknesses of the first oxide film 20a and the second oxide film 20b constituting the insulating film 20 cannot be the same due to the aforementioned reasons, the EPROM cell When a high voltage is applied to the control gate during driving, due to the difference in thickness, a part of electrons filled in the floating gate 10 exits to the control gate 30, a so-called charge loss phenomenon occurs. If this phenomenon occurs, a defect in which the overall operating characteristics of the EPROM cell is degraded is caused, and an improvement for this problem is urgently required.
이에 본 발명의 목적은, EPROM 셀을 이루는 ONO 구조의 절연막 형성시 질화막 상에 형성되는 제 2 산화막을 산화 공정이 아닌 CVD법과 어닐링(annealing) 공정을 적용하여 형성해 주므로써, 공정 진행상의 어려움없이도 제 1 산화막과 제 2 산화막을 동일한 두께로 가져갈 수 있도록 하여 EPROM 셀 구동시 야기되던 차지 로스 현상을 현격하게 줄일 수 있도록 한 EPROM 셀 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a second oxide film formed on the nitride film during the formation of the ONO structure of the EPROM cell by applying the CVD method and the annealing process instead of the oxidation process. The present invention provides a method for forming an EPROM cell in which the first oxide film and the second oxide film can have the same thickness, thereby significantly reducing the charge loss caused when the EPROM cell is driven.
도 1은 종래의 EPROM 셀 구조를 도시한 단면도,1 is a cross-sectional view showing a conventional EPROM cell structure;
도 2는 도 1에 제시된 EPROM 셀 형성방법을 도시한 공정 블록도,FIG. 2 is a process block diagram illustrating a method of forming an EPROM cell shown in FIG. 1;
도 3는 본 발명에 의한 EPROM 셀 형성방법을 도시한 공정 블록도이다.3 is a process block diagram illustrating a method of forming an EPROM cell according to the present invention.
상기 목적을 달성하기 위하여 본 발명에서는, 반도체 기판 상의 소정 부분에 플로팅 게이트를 형성하는 공정과; 상기 플로팅 게이트를 포함한 상기 기판 상에 제 1 산화막을 형성하는 공정과; 상기 제 1 산화막 상에 질화막을 형성하는 공정과; CVD 공정을 이용하여 상기 질화막 상에 제 2 산화막을 형성하고, 이를 어닐링하는 공정; 및 상기 플로팅 게이트 상측의 상기 제 2 산화막 상에 컨트롤 게이트를 형성하는 공정으로 이루어진 EPROM 셀 형성방법이 제공된다.In order to achieve the above object, the present invention includes the steps of forming a floating gate on a predetermined portion on a semiconductor substrate; Forming a first oxide film on the substrate including the floating gate; Forming a nitride film on said first oxide film; Forming a second oxide film on the nitride film by using a CVD process and annealing the second oxide film; And forming a control gate on the second oxide film on the floating gate.
상기와 같이 EPROM 셀을 형성한 결과, 공정 진행상의 어려움없이도 절연막을 이루는 제 1 산화막과 제 2 산화막의 두께를 거의 동등한 순준으로 가져갈 수 있게된다.As a result of forming the EPROM cell as described above, the thicknesses of the first oxide film and the second oxide film constituting the insulating film can be brought to almost equal levels without difficulty in process progression.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3은 본 발명에 의한 EPROM 셀 형성방법을 도시한 공정 블록도를 나타낸 것으로, 이를 참조하여 그 형성벙법을 크게 제 3 단계로 구분하여 살펴보면 다음과 같다.3 is a process block diagram illustrating a method of forming an EPROM cell according to the present invention. Referring to this, a method of forming the EPROM cell is divided into three steps.
제 1 단계(200)로서, 반도체 기판 상에 폴리실리콘 재질의 제 1 도전성막을 형성하고, 상기 기판 표면이 소정 부분 노출되도록 이를 선택식각하여 플로팅 게이트(10)를 형성한다.As a first step 200, a first conductive layer of polysilicon is formed on a semiconductor substrate, and the substrate is selectively etched to expose a portion of the substrate to form a floating gate 10.
제 2 단계(202)로서, 상기 플로팅 게이트(10)를 포함한 상기 기판 상에 80 ~ 90Å 두께의 제 1 산화막(20a)을 형성한 뒤, 120 ~ 140Å 두께의 질화막(20b)을 형성하고, 그 위에 다시 80 ~ 90Å의 두께의 제 2 산화막(20c)을 형성해 주어 ONO(제 1 산화막(20a)/질화막(20b)/제 2 산화막(20c)) 적층 구조의 절연막(20)을 형성한다.As a second step 202, after forming the first oxide film 20a having a thickness of 80 to 90 kPa on the substrate including the floating gate 10, a nitride film 20b having a thickness of 120 to 140 kPa is formed. A second oxide film 20c having a thickness of 80 to 90 kV is formed again on it to form an insulating film 20 having an ONO (first oxide film 20a / nitride film 20b / second oxide film 20c) laminated structure.
이때, 제 1 산화막(20a)은 850℃의 온도에서 산화 공정을 거쳐 형성되고, 질화막(20b)은 CVD 공정에 의해 형성되며, 제 2 산화막(20c)은 CVD 공정을 이용하여 막질을 증착한 후 N2분위기하에서 어닐링 공정을 실시해 주는 방식으로 형성된다. 이와 같이, 제 2 산화막(20c) 형성시 별도의 어닐링 공정을 더 실시해 준 것은 최종적으로 만들어진 제 2 산화막(20c)이 산화 공정을 거쳐 형성된 제 1 산화막(20a)과 유사한 막질 특성을 가지도록 하기 위함이다.In this case, the first oxide film 20a is formed through an oxidation process at a temperature of 850 ° C., the nitride film 20b is formed by a CVD process, and the second oxide film 20c is deposited by using a CVD process. It is formed in such a manner that the annealing process is performed under an N 2 atmosphere. As such, the additional annealing process is further performed when the second oxide film 20c is formed so that the finally formed second oxide film 20c has a film quality similar to that of the first oxide film 20a formed through the oxidation process. to be.
이러한 공정을 거쳐 제 2 산화막(20c)을 형성할 경우, 공정 진행상의 어려움이나 혹은 제 2 산화막(20c)의 막질 특성 저하없이도 용이하게 제 1 산화막(20a)과 제 2 산화막(20c)을 동일한 두께로 형성할 수 있게 되므로, 이후 EPROM 셀 구동시 제 1 및 제 2 산화막(20a),(20c)의 두께 차이로 인해 야기되던 차지 로스 현상을 최대한 억제할 수 있게 된다.When the second oxide film 20c is formed through such a process, the first oxide film 20a and the second oxide film 20c have the same thickness easily without difficulty in the process or deterioration of the film quality characteristics of the second oxide film 20c. Since it can be formed, the charge loss phenomenon caused by the difference in thickness between the first and second oxide films 20a and 20c during the EPROM cell driving can be suppressed as much as possible.
제 3 단계(204)로서, 상기 절연막(20) 상에 폴리사이드 재질의 제 2 도전성막을 형성하고, 상기 플로팅 게이트(10) 양 에지측 상의 상기 절연막(20) 표면이 소정 부분 노출되도록 이를 선택식각하여 컨트롤 게이트(30)를 형성하므로써, 본 공정 진행을 완료한다.In a third step 204, a second conductive film of polyside material is formed on the insulating film 20, and the etching is performed so that a predetermined portion of the surface of the insulating film 20 on both edges of the floating gate 10 is exposed. By forming the control gate 30, the process progress is completed.
이상에서 살펴본 바와 같이 본 발명에 의하면, ONO 구조의 절연막 형성시 질화막 상에 형성되는 제 2 산화막을 CVD 공정과 어닐링 공정을 이용하여 형성해 주므로써, 제 2 산화막의 막질 특성 저하없이도 제 1 산화막과 제 2 산화막을 거의 동등한 수준의 두께로 가져갈 수 있게 되므로, 상기 절연막을 이루는 제 1 및 제 2 산화막의 두께 차이로 인해 야기되는 차지 로스 현상을 막을 수 있게 되어 고신뢰성의 EPROM 셀을 구현할 수 있게 된다.As described above, according to the present invention, the second oxide film formed on the nitride film during the formation of the ONO structure insulating film is formed by using the CVD process and the annealing process, so that the first oxide film and the second oxide film are not degraded. Since the second oxide film can be approximately equal in thickness, it is possible to prevent the charge loss caused by the difference in thickness between the first and second oxide films constituting the insulating film, thereby realizing a highly reliable EPROM cell.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980022052A KR20000001682A (en) | 1998-06-12 | 1998-06-12 | Method of forming eprom cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980022052A KR20000001682A (en) | 1998-06-12 | 1998-06-12 | Method of forming eprom cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000001682A true KR20000001682A (en) | 2000-01-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980022052A KR20000001682A (en) | 1998-06-12 | 1998-06-12 | Method of forming eprom cell |
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| Country | Link |
|---|---|
| KR (1) | KR20000001682A (en) |
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1998
- 1998-06-12 KR KR1019980022052A patent/KR20000001682A/en not_active Application Discontinuation
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