KR100237007B1 - Fabrication method of flash memory cell - Google Patents

Abstract

The present invention relates to a flash memory cell manufacturing method.

The present invention does not completely remove the field oxide layer in the source field region during the self-aligned source etching process in order to prevent etching damage of the tunnel oxide layer during the self-aligned source etch process of the flash memory cell. After leaving it to some extent, a source impurity ion implantation process is then performed to form a source line.

Description

Manufacturing Method of Flash Memory Cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to prevent etching damage of a tunnel oxide film generated during self-aligned source etch of a flash memory cell, thereby improving cell reliability and endurance. A flash memory cell manufacturing method that can be improved.

In general, a self-aligned source etching process is applied to reduce a source line dimension in a stack type flash memory cell.

1 is a layout diagram of a conventional flash memory cell, Figures 2 (a) to (c) is a cross-sectional view of the element cut along the line X2-X2 of Figure 1 to explain a conventional flash memory cell manufacturing method, Figure 3 (a) to (c) are cross-sectional views of devices cut along the lines Y3-Y3 of FIG. 1 to explain a conventional flash memory cell manufacturing method.

2 (a) and 3 (a), the field oxide film 2 is formed on the semiconductor substrate 1 through an isolation process. Through a general process, a stacked gate in which the floating gate 4 and the control gate 6 are stacked is formed. A tunnel oxide film 3 is formed between the floating gate 4 and the semiconductor substrate 1. A dielectric film 5 is formed between the floating gate 4 and the control gate 6. In the dielectric film 5, an oxide-nitride-oxide (ONO) structure is widely applied. An insulating film 7 for protecting the control gate 6 is formed on the control gate 6. The insulating film 7 is formed mainly by depositing an oxide film by chemical vapor deposition.

Referring to FIGS. 2B and 3B, after forming a photoresist pattern 100 having an open area where a source line is to be formed, a field is formed by a self-aligned source etching process using the photoresist pattern 100 as an etching mask. The exposed portion of the oxide film 2 is etched. The self-aligned source etching process uses anisotropic etching, where the edge portion of the tunnel oxide film 3, which is the lower layer of the floating gate 4, is etched and damaged while the field oxide film 2 of the exposed portion is removed. 10) will be produced.

2 (c) and 3 (c), the drain 8 and the source line 9 are formed by removing the photoresist pattern 100 and then performing a source / drain impurity implantation process. The source line 9 is formed by interconnecting a source active region 9A and a source field region 9B.

According to the above process, etching damage such as the undercut 10 occurs in the tunnel oxide film 3 during the self-aligned source etching process, and thus there is a problem in that reliability during the erase operation is lowered.

To solve this problem, before removing the field oxide film of the source field region, impurities are first injected into the source active region, a cell spacer is formed on the side of the stacked gate, and then a self-aligned source etching process is performed. The local field oxide film is removed, and impurities are entirely injected to form source lines. Although this method can prevent the etching damage of the tunnel oxide layer described above, there is a problem that bottlenecks occur in current flow because the sheet resistance of the source active region and the sheet resistance of the source field region are different.

Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory cell that can improve the reliability and durability of the cell by solving the above-described problems generated during the manufacture of a flash memory cell to which a self-aligned source etching process is applied.

The present invention for achieving this object comprises the steps of forming a stacked gate consisting of a floating gate and a control gate on a semiconductor substrate formed with a field oxide film; Performing a self-aligned source etching process so that the field oxide film in the source field region remains constant; And forming a drain and a source line by an ion implantation process.

1 is a layout diagram of a conventional flash memory cell.

2 (a) to 2 (c) are cross-sectional views of devices cut along the line X2-X2 of FIG. 1 to explain a conventional flash memory cell manufacturing method.

3A to 3C are cross-sectional views of devices cut along the line Y3-Y3 of FIG. 1 to explain a conventional flash memory cell manufacturing method.

4 is a layout diagram of a flash memory cell of the present invention.

5A to 5C are cross-sectional views of devices cut along the lines X5-X5 of FIG. 4 to illustrate a method of manufacturing a flash memory cell according to an embodiment of the present invention.

6 (a) to 6 (c) are cross-sectional views of devices cut along the line Y6-Y6 of FIG. 4 to illustrate a method of manufacturing a flash memory cell according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 and 11: semiconductor substrate 2 and 12: field oxide film

3 and 13: tunnel oxide film 4 and 14: floating gate

5 and 15: dielectric film 6 and 16: control gate

7 and 17: insulating film 8 and 18: drain

9 and 19: source lines 9A and 19A: source active region

9B and 19B: Source Field Region 10: Undercut

20: oxide film 100 and 200: photosensitive film pattern

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 is a layout diagram of a flash memory cell of the present invention, Figure 5 (a) to (c) is cut along the line X5-X5 of Figure 4 to explain a method of manufacturing a flash memory cell according to an embodiment of the present invention. 6 (a) to 6 (c) are cross-sectional views of a device taken along the line Y6-Y6 of FIG. 4 to explain a method of manufacturing a flash memory cell according to an embodiment of the present invention.

5 (a) and 6 (a), the field oxide film 12 is formed on the semiconductor substrate 11 through an isolation process. The floating gate 14 and the control gate 16 are formed in a stacked structure. A tunnel oxide film 13 is formed between the floating gate 14 and the semiconductor substrate 11. A dielectric film 15 is formed between the floating gate 14 and the control gate 16. In the dielectric film 15, an oxide-nitride-oxide (ONO) structure is widely applied. An insulating film 17 for protecting the control gate 16 is formed on the control gate 16. The insulating film 17 is mainly formed by depositing an oxide film by chemical vapor deposition. The thermal oxidation process is performed to grow the oxide film 20 on the exposed portion of the semiconductor substrate 1 and the exposed portion of the stacked gate. The oxide film 20 is formed by performing a thermal oxidation process up to a point where the test wafer is oxidized to a thickness of 50 to 70 GPa.

Referring to FIGS. 5B and 6B, after forming a photoresist pattern 200 having an open area where a source line is to be formed, a field is formed by a self-aligned source etching process using the photoresist pattern 200 as an etching mask. The exposed portion of the oxide film 12 is etched to a predetermined depth to form a residual field oxide film 12B, at which time the exposed oxide film 20 is also removed. When the thickness of the field oxide film 12 is 3000 to 3800 kPa, the etching is performed so that the thickness of 500 to 800 kPa remains. In the self-aligned source etching process, anisotropic etching is applied.

Referring to FIGS. 5C and 6C, after the photoresist pattern 200 is removed, a source / drain impurity implantation process may be performed with the remaining field oxide film 12A in the source field region 19B, thereby draining the drain ( 18 and source line 19 are formed. The source line 19 is formed by interconnecting the source active region 19A and the source field region 19B.

Before the field oxide film 12 is etched by the self-aligned source etching process, the oxide film 20 is formed by the thermal oxidation process, and the self-aligned source etching is not performed by completely etching the field oxide film 12 during the self-aligned source etching process. The tunnel oxide layer 13 is not etched during the process. On the other hand, a slight resistance difference occurs between the source active region 19A and the source field region 19B by implanting source impurity ions while the source field region 19B has the remaining field oxide film 12A in the source field region 19B. Since the oxide film 12A remains in a thin thickness, it does not significantly affect the electrical characteristics of the device.

As described above, the present invention protects the tunnel oxide layer by a thermal oxidation process before the self-aligned source etching process, and by etching to leave a certain thickness of the field oxide layer in the source field area during the self-aligned source etching process, thereby preventing etching damage of the tunnel oxide layer. It is possible to improve the reliability and durability of the cell.

Claims (3)

Forming a stacked gate comprising a floating gate and a control gate on a semiconductor substrate on which a field oxide film is formed; Performing a self-aligned source etching process so that the field oxide film in the source field region remains constant; A method of manufacturing a flash memory cell, comprising forming a drain and a source line by an ion implantation process. The method of claim 1, wherein the self-aligned source etching process is performed such that the thickness of the field oxide layer is 500 to 800 μm when the thickness of the field oxide layer is 3000 to 3800 μs. The method of claim 1, further comprising forming an oxide layer to prevent etching damage of the tunnel oxide layer by performing a thermal oxidation process before the self-aligned source etching process.

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