JPS59154068A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacitance between the first and second gate electrodes and thus contrive to reduce the write voltage by a method wherein the first gate electrode is projected on an element isolation region in an almost vertical direction to a substrate, and the second gate electrode is provided on this first gate electrode via the second gate insulation film. CONSTITUTION:A PROM memory cell has a structure having the first gate electrode 21 which crosses a part of the element isolation region 13 via the first gate oxide film 20 and has the form that both ends extending on a field oxide film 12 are projecting in a vertical direction to the surface of the substrate 11 and the second gate electrode 23 laminated on said electrode 21 via the second gate oxide film 22. Thereby, since the surface area of the first gate electrode 21 to the second gate electrode 23 can be increased, the capacitance between the first and second gate electrodes 21 and 23 can be increased. Therefore, the write voltage into the second gate electrode 23 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[Technical background of the invention]

Nonvolatile semiconductor memory devices, such as FROM (Progr.
amable Read Only Memory)
Conventionally, memory cells having the structure shown in FIGS. 1 and 2 are known. That is, 1 in the figure is a P-type semiconductor substrate, and this substrate 1 is provided with a field oxide film (element isolation region) 3 for isolating element regions 2. As shown in FIG. This element region 2 has n
Additional source and drain regions 4, 5 are provided. A first dirt electrode (floating gate electrode) 7 made of, for example, impurity-doped polycrystalline silicon is provided on a portion of the device region 2 including the channel region between these source and drain regions 4 and 5 via a first dirt insulating film 6. It is provided. Furthermore, a second dirt electrode (control gate electrode) 9 made of, for example, impurity-doped polycrystalline silicon is laminated on the first part electrode 7 with a second dirt insulating film 8 interposed therebetween. Note that both ends of the first dirt electrode 7 extend in the channel width direction, and parts of these ends overlap on the field oxide film 3. In addition, the first
An insulating film 10 is formed on the exposed side surface of the dirt electrode 7 and on the concave circumference of the second dirt electrode 9. In such a FROM, hot carriers generated in the channel region by applying a high voltage to the second dirt electrode 9 and the male drain region 5 are transferred to the first dirt electrode 7 through the first dirt insulating film 6.
By injecting and accumulating the ions and changing the threshold voltage (V), a predetermined memory cell retains its memory function.

By the way, in the above-mentioned FROM shown in FIGS. 1 and 2, the electrical circuit at the time of writing is shown schematically as shown in FIG. There is a relationship between VCC as shown in the following formula.

Here, C1 is the capacitance between the substrate 1 and the electrode 70, C2 is the capacitance between the floating gate electrode 7 and the control gate electrode 9, and C3 is the capacitance between the drain region 5 and the floating gate electrode 7. Capacitance/vD indicates drain voltage.

Writing into the FROM is determined by the voltage VFG of the floating gate electrode 7, and what actually controls VFG is the voltage VCO of the control dart electrode 9. That is, VFG
The proportionality coefficient between and VCC is C2/cT, and in order to be able to write at a low voltage, simply increasing the capacitance C2 between the floating gate electrode 2 and the control gate electrode 9 is sufficient.

[Problems with background technology]

However, in the prior art, a so-called write voltage, which is applied to the control gate electrode even in a 64 EFROM device, requires a high voltage of 21V. In particular, as devices become smaller in the future, lower write voltages will be required. Therefore, one possible method for increasing the capacitance C2 between the dirt electrodes is to make the second dirt insulating film 8 shown in FIG. That is difficult.

[Purpose of the invention]

The present invention aims to provide a semiconductor memory device and a method for manufacturing the same, which can increase the capacitance between the first and second dart electrodes without causing deterioration of device characteristics, and further reduce the write voltage. .

[Summary of the invention]

In the present invention, the first dirt electrode is made to protrude substantially perpendicularly to the substrate on the element isolation region, and the second dirt electrode is provided on the first dirt electrode with a second dirt insulating film interposed therebetween. ．． The main idea is to increase the capacitance between the second gate electrodes and reduce the write voltage.

That is, the invention of Application No. 1 provides a semiconductor memory device including two or more layers of dirt electrodes in an island region of a semiconductor substrate separated by an element isolation region, in which a first dirt electrode covers a part of the island region. A second dirt electrode is formed on the region including the first dart electrode, and has a shape in which the vicinity of the end extending across the first dart insulating film and extending onto the element isolation region protrudes in a direction substantially perpendicular to the substrate surface. This is characterized in that the dirt electrode is provided via a second dirt insulating film.

As the dirt electrode material, for example, polycrystalline silicon containing impurities, amorphous silicon containing impurities, high melting point metal silicide such as molybdenum silicide, tungsten silicide, platinum silicide, etc. can be used.

Further, the invention of Application No. 2 provides a method for manufacturing a semiconductor memory device having two or more layers of dart electrodes in an island-like region of a semiconductor substrate separated by an element isolation region. a step of forming a thick film pattern made of an insulating material in the separation region, and a first dart electrode that is covered with the island-like region via a first insulating film and has at least an end overlapped with the film and the main pattern. a step of forming an electrode material pattern, a step of removing the coating A-turn, and depositing a second gate electrode material over the entire area including the electrode material pattern via a second insulating film formed around the pattern. and selectively etching away at least at least the second dirt electrode material film to the electrode material pattern to form a third electrode material having a shape in which the vicinity of the end portion above the element isolation region protrudes in a direction substantially perpendicular to the substrate surface. The method is characterized by comprising a step of forming a first dirt electrode, a second gate insulating film, and a second dirt electrode.

The coating film serves to cause the end portion of the electrode material pattern, which will become the first dirt electrode, to protrude in a direction substantially perpendicular to the substrate surface. For this reason, active ion etching (RIE) is used when forming films and patterns.
) or the like to form a steep side surface of the portion where the electrode material patterns overlap. The material for the overcast coating iR turn is 5to2.5i5N4 or A7203.
Insulating materials such as

The step of forming a second insulating film around the electrode material pattern can be performed by thermal oxidation when the same pattern is made of polycrystalline silicon or amorphous silicon.

[Embodiments of the invention]

Next, a manufacturing process for illustrating a FROM memory cell, which is an embodiment of the present invention, will be described in detail.

(1) First, a field oxide film (element isolation region) 12 is formed by, for example, selective conversion of a P-type silicon substrate 11, and then a 5i02 film with a thickness of about 1 μm is deposited on the entire surface by CVD.
After being deposited using the D method, it is patterned using a photoetching technique using RIE to open the periphery including the element region 13, and form 5i02 with a steep inner surface of the opening.
A pattern 15 was formed on the field oxide film 12 (as shown in FIG. 4(a)). A first thermal oxide film 14 having a thickness of 500× and becoming a first dirt oxide film was formed by thermal oxidation on the surface of an island region (device region) 13 of the substrate 11 separated by a field oxide film 12.

(11) Next, after forming a phosphorus-doped polycrystalline silicon film 16 with a thickness of, for example, 4000× on the entire surface, a resist pattern 17 is formed on the polycrystalline silicon film 16 by photolithography.
was formed (as shown in FIG. 4(b)).

Subsequently, polycrystalline silicon film 16 was selectively etched using resist pattern 17 as a mask. As a result, as shown in FIG. 4(c), 3iQ2-J? turn 15
A polycrystalline silicon pattern 18 was formed which overlapped a portion of the pattern and had a defined length in the channel width direction.

(IIl) Next, after removing the resist pattern 17, the \5to2 pattern 15 was removed using an ammonium fluoride solution or the like. Subsequently, a thermal oxidation treatment was performed to form a second thermal oxide film 19 with a thickness of 800X around the polycrystalline silicon pattern 18 (as shown in FIG. 4(d)).

(iV1) Next, a phosphorus-doped polycrystalline silicon film with a thickness of, for example, 4000X was deposited on the entire surface, and it was sufficiently wrapped around the polycrystalline silicon pattern portion where the 5to2/guturn 15 was removed.Subsequently, this polycrystalline silicon film was (Renos is applied to the second dart electrode forming part by photolithography)
1? After forming a turn (not shown), the phosphorus-doped polycrystalline silicon film, second thermal oxide film, polycrystalline silicon/, O-turn, and first thermal oxide film were selectively removed by RIE using the resist pattern as a mask. . As a result, from the substrate 11 side, the first gate oxide film 20, the first dart electrode (floating gate electrode) 21 having both ends protruding near the field oxide film 12 in a direction substantially perpendicular to the surface of the substrate 11, and the first dirt electrode (floating gate electrode) 21 are formed. A second cage is laminated on the dirt electrode 21 with a second dirt oxide film 22 interposed therebetween, and has both ends extending in the channel width direction on the field oxide film 12.
A gate electrode (control gate electrode) 23 was formed.

Subsequently, after removing the resist pattern, using the second dirt electrode 23 and field oxide film 12 as a mask, an n.
A type impurity such as arsenic was ion-implanted, activated, and diffused to form double-type source and drain regions 24 and 25, thereby manufacturing a FROM memory cell (as shown in FIGS. 4(e) and 5). . Incidentally, FIG. 5 is a plan view of the fourth embodiment.

Therefore, the memory cell of the FROM of the present invention is shown in FIG.
) and the element region 1 of the silicon substrate 11 as shown in FIG.
a first dirt electrode 21 having a shape in which both ends thereof protrude perpendicularly to the surface of the substrate 11;
The structure includes a second dirt electrode 23 laminated on the first dirt electrode 21 with a second dirt oxide film 22 interposed therebetween. However, compared to the conventional memory cell shown in FIG. 1, the red area of the first gate electrode 21 relative to the second gate electrode 23 can be increased. The capacitance between the second dart electrodes 21 and 23 can be increased. In fact, the capacitance in this embodiment is 02', and the first . When the capacitance between the second gate electrode is 02, C2'# 1.7 C
2', and the capacity can be increased compared to the conventional one. Therefore, the write voltage to the second dart electrode 23 can be reduced,
In turn, it is possible to lower the voltage in response to miniaturization. Furthermore, when the capacitance is the same as that of the conventional structure, it is possible to reduce the area of the floating gate electrode 21, and further miniaturize the element (memory cell).

Further, according to the present invention, the first. 2nd dart electrode 21.23
Since it is not necessary to make the second gate oxide film 22 between the electrodes 21 and 23 thinner in order to increase the capacitance between them, a decrease in breakdown voltage can be avoided.

Furthermore, according to the method of the present invention, a thick 5i02 pattern 15 is formed on the field oxide film 12, and the thick turn 15 is formed on the field oxide film 12.
An electrode material pattern arch 8 that will become a first dirt electrode is formed so as to overlap thereon, and then the sto'2 pattern 15 is removed and the electrode pattern 18 is patterned so that both ends of the field oxide film 12 are brought to the surface of the substrate 11. The first dirt electrode 21 having a large surface area and protruding in a substantially perpendicular direction can be easily formed. Moreover, by changing the film thickness of the 5i02 pattern (coating pattern) 15,
The protruding height of the end of the first gate electrode on the field oxide film can be adjusted arbitrarily, and the height of the first gate electrode end can be adjusted as desired. Second dirt electrode 21
．． Capacity between 23 can be easily controlled.

In the above embodiment, a thermal oxide film formed by thermal oxidation of the first dirt electrode made of phosphorus-doped polycrystalline silicon was used as the material for the second gate insulating film, but CVD-8
An i02 film may also be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, the first. It is possible to provide a semiconductor memory device in which the capacitance between the second dart electrodes can be increased and a write voltage can be reduced, as well as a method for easily manufacturing such a semiconductor memory device.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional FROM memory cell, Fig. 2 is a cross-sectional view of the two-layer dirt electrode section of the memory cell of Fig. 1 cut in the channel length direction, and Fig. 3 is a cross-sectional view of a FROM memory cell. Schematic diagrams schematically showing electrical circuits during writing, FIGS. 4(a) to 4(e) are F in the embodiment of the present invention.
FIG. 5 is a cross-sectional view showing the manufacturing process of a ROM memory cell, and FIG. 5 is a plan view of FIG. 4(e). 11...P-type silicon substrate, 12...Field"
Oxide film (element isolation region 9), 13... element region, 15.
...5i02 pattern, 18...polycrystalline silicon 1?
turn, 20...first dirt oxide film, 21...first
Dart electrode (floating gate electrode), 22...
second dirt oxide film, 23... second gate electrode (control gate electrode), 24... n increased source region, 2
5...n drain region.

Claims (1)

[Claims] (1) In a semiconductor memory device having two or more layers of gate electrodes in an island region of a semiconductor substrate separated by an element isolation region, the first gate electrode covers a part of the island region. The vicinity of the end portion extending across the first dirt insulating film and extending onto the element isolation region has a shape protruding in a direction substantially perpendicular to the substrate surface, and a first dirt insulating film is formed on the region including the first gate electrode. A semiconductor memory device characterized in that a two-gate electrode is provided with a second dirt insulating film interposed therebetween. (2) In the manufacture of a semiconductor memory device having two or more layers of gate electrodes in an island region of a semiconductor substrate separated by an element isolation region, the element isolation region portion located at least near the island region of the semiconductor substrate a step of forming a thick film or pattern made of an insulating material on the island; and a first gate electrode that is covered with a first insulating film on the island-like region and has at least an end portion overlapping with the pattern of the film. a step of forming an electrode material pattern, a step of removing the film pattern, and a step of depositing a second gate electrode material over the entire area including the electrode material pattern through a second insulating film formed around the pattern. at least a step of
The parts from the two-gate electrode material film to the electrode material/mother turn are sequentially and selectively etched away to form a first dirt having a shape in which the vicinity of the end above the element isolation region protrudes in a direction substantially perpendicular to the substrate surface. A method for manufacturing a semiconductor memory device, comprising the steps of forming an electrode, a second dirt oxide film, and a second dirt electrode. (3) The method of manufacturing a semiconductor memory device according to claim 2, wherein the insulating material is 5i02 or Si3N4. (4) If the electrode material/mother turn is made of impurity-doped polycrystalline silicon or impurity-doped amorphous silicon, a second insulating film is formed around the pattern by thermally oxidizing the electrode material pattern. A method of manufacturing a semiconductor memory device according to claim 2, characterized in that: (5) The method of manufacturing a semiconductor memory device according to claim 2, wherein the film pattern is formed by selective etching using active ion etching and has steeply shaped side surfaces.