JPS6317551A - Integrated circuit and manufacture of the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an integrated circuit and a method of manufacturing the same.

[Conventional technology]

Very large scale integrated circuit (VSL) nonvolatile storage devices and other high voltage integrated circuits typically use two polycrystalline silicon layers with a suitable dielectric thin film layer between these two polycrystalline layers. This meets the requirements of maintaining a high electric field and minimizing VC leakage current. Traditionally, polycrystalline silicon is deposited by low pressure chemical vapor deposition (LPCVD) at approximately 620°C. The dielectric thin film layer may be thermally grown on the polycrystalline (1) layer or may be a composite thin film layer of oxide/nitride/oxide.

Many types of integrated circuit structures Kj? The smoothness of the interface between polycrystalline silicon and the dielectric in polycrystalline-to-polycrystalline capacitors is critical, especially in non-volatile erasable memory devices (hereinafter referred to as EPROMs) and electronic erasable memory devices (hereinafter referred to as EEFROMs). . That is, it has been found that when an oxide is grown on polycrystalline silicon, the polysilicon-to-dielectric interface typically has a significant degree of roughness. As is well known, this roughness leads to field enhancement and, therefore, to prevent breakdown, the dielectric thickness is as large as would be necessary if this interface were perfectly smooth and flat. It must be made much thicker than wax. Although the prior art has attempted to find solutions to the problem of achieving smooth polycrystalline and dielectric interfaces,
No notable successes have been achieved.

The most important documents known to the applicant in this technical field are listed below, all of which are incorporated by reference in this application.

- El 7 Alaon, Improved Manufacturing Processes for Multilevel Polycrystalline Silicon Structures, RCA Laboratories (L.

Faraone, An Improved Fab
Process for Multi
-Level Polysilicon 5truct
ure) (date not given; apparently identical but not published).

・ Harbeke et al.: LPCVD polycrystalline silicon: in-situ lindoso and V-less thin film growth and physical properties, 44RCA Review 287 (July 1983) (Harbekee
t aL , , LPCVD Polycrysta
lline 5ilicon: Growthand
Physical Property of I
n-81tu PhosphorusDoped an
d Undoped Films, 44 RCA
REVIEW287 (June 1983).

・ Chiao et al., Development of thin film polycrystalline oxide for non-volatile memory devices, Semiconductor International, April 1985, pp. 156-159 (chiao at at
, , Developments in Th1nP
olyoxides for Non-Volatil
e Memories.

sEMrcoNnUcToRENGNTgRNATxoNA
, April 1985, Pages 156-15
9) Faraone et al., Characteristic analysis of thermally oxidized n+ polycrystalline silicon, 62° Institute of Electrical and Electronics Engineers Technical Report, Electronic Devices (March 1985) (Faraone ataL,...
Characterization of Th
permanently Oxidizedn”Polycr
ystalline 5ilicon, 32 IE
EE Tran-aaction on Electr
on Devices (March 1 985
).

The most useful teaching of the prior art appears to be Faraon's paper published in Institute of Electrical and Electronics Engineers (EEE) Technical Report: Electronic Devices. This paper makes the important proposition that the lower polycrystalline silicon layer should be deposited as an amorphous layer rather than as a polycrystalline silicon layer to improve interfacial smoothness. Contains.

That is, as is well known in the art, by lowering the temperature at which polycrystalline silicon is deposited from, for example, 625° C. to, for example, 562° C., the thin film then deposited is no longer polycrystalline and is effectively amorphous. become. Amorphous thin films initially have significantly flatter surfaces than polycrystalline thin films, but this is simply because, in polycrystalline thin films, grain boundaries and various orientations of grains account for some initial surface roughness. This is because they tend to occur.

[Problem that the invention seeks to solve]

However, the important teaching of the present invention, which is not contained in any known literature, is that after the first layer of amorphous material is deposited, it is not oxidized. Instead, a deposited fat electrolyte is used. The reason for this is that the oxidation treatment deteriorates the surface shape, and the reason is not simply thermal.
The oxidation process involves oxidation-assisted diffusion along grain boundaries, and this grain boundary diffusion itself causes roughness. Therefore, chemical vapor deposition of good quality dielectrics typically proceeds at temperatures only slightly lower than those used in the sufficiently low oxidation step, but as a result the interfacial smoothness is greatly improved, and This is because migration of oxygen along grain boundaries is substantially avoided. Thus, the present invention provides a much smoother interface than was possible with any prior art method.

Additionally, it should be noted that the prior art proposals for smooth interfaces do not provide a process as well suited for manufacturing as the present invention does. That is, prior art processes tend to require very fine control over the temperatures used in the low temperature oxidation step, and such tight control therefore harms manufacturing capacity. Therefore, another advantage of the present invention is improved manufacturability.

Moreover, a further teaching of the present invention is that the silicon layer is doped by implantation rather than by diffusion (e.g., using PO (using J3). The implantation process includes It further amorphizes the deposited silicon layer and thus further contributes to maintaining fine grain size within this layer after the relatively high temperature dielectric deposition step.

It should be noted that whether using the prior art oxidation process or the deposited dielectric process of the present invention, some grain growth will occur during the high temperature stage. A surprising result of the present invention is that as a result of this grain growth, the amorphous, now deposited layer is converted into a polycrystalline layer while still maintaining an extremely smooth surface.

In certain embodiments of the invention, the deposited dielectric is arranged as an oxide/nitride layered dielectric, which is further thermally oxidized to form an oxide/nitride. /oxide layered structure, and this dielectric is particularly effective in holding the first polycrystalline conductive interface in place during thermal cycling.

It should also be noted that the only known editorial addressing ion implantation as opposed to V-Zo by diffusion is listed in reference (21) in the article by Faraone. This is seen in the correspondence of 7 Araon. A copy of this has been submitted to the Examiner's Reference Materials, but it should be noted that this editorial has never been published and therefore is It will not be recognized as a formal reference under the patent systems of at least some of the countries in which it is intended.

The present invention therefore provides a decisive improvement in interfacial quality over all known art methods and structures. This results in a capacitor in which the bottom plate is made of polycrystalline silicon and a predominantly silicon layer, in which the breakdown voltage for a given thickness of dielectric is improved (usually acceptable). To use the figure of merit which is calculated as follows, the stored charge per unit area on this capacitor - 1t - can be significantly improved.

In particular, the invention is extremely advantageous in connection with KFROM cells. It is always desirable that the coupling between the floating r-) and the controlled r-) be as tight as possible, but the so-called interlayer dielectric between the polycrystals must not break down under the working voltage. In order to maintain a sufficient storage life, and also to maintain a sufficient storage life, the dielectric must have a very low leakage current. The present invention has the advantage that by reducing the roughness of the interface between the polycrystalline layer and the dielectric, it not only improves the breakdown voltage value but also reduces the leakage current at a voltage lower than the breakdown voltage. .

Therefore, an EPROM or EEPROM constructed in accordance with the present invention has significant advantages and significantly outperforms all available prior art implementations with respect to coupling of control and floating dates and crossing currents.

In addition to the other advantages mentioned in section h of this application, the invention has at least the following advantages: These are: - Manufacturing processes with improved reproducibility - Low leakage currents through the interlayer capacitors - High breakdown voltages in the interlayer capacitors - The ability to provide high capacitance ratios for glabellar capacitors with a given breakdown voltage.

- The ability to manufacture floating date storage transistors of a given density for high speed programming.

[Means to solve the problem]

According to the invention, an integrated circuit capacitor is obtained, which comprises: a first polycrystalline conductive layer containing more than 5 degrees of silicon atoms; a composite dielectric covering the top surface of the first conductive layer; , a second conductive layer covering the top surface of the dielectric, and a voltage of at least four times the voltage required to break down the dielectric if it were an ideal dielectric with that layer thickness. and a device for applying a voltage corresponding to - to the capacitor.

According to the present invention, the following nonvolatile memory cell can also be obtained. That is, the cell includes a transistor channel region, a floating r−) overlying and capacitively coupled to the transistor channel region, a control date capacitively coupled to the floating date, and a control date capacitively coupled to the floating date. The control r-) is capacitively coupled to this floating date through a dielectric with a maximum local excursion of 80 perpendicular to the interface.

According to the present invention, the following nonvolatile memory cell can also be obtained. That is, this cell includes a transistor channel region, a floating date overlying and capacitively coupled to this transistor channel region, a control r-) capacitively coupled to this floating The control data is capacitively coupled through the dielectric with a maximum local excursion perpendicular to the interface, corresponding to 10 cm of the thickness of this dielectric.

In accordance with the present invention, there is also provided a process for manufacturing a non-volatile storage cell, which process includes the steps of: creating a semiconductor substrate; forming a date insulating film over predetermined locations of a non-volatile storage transistor; depositing a first conductive layer containing more than 50% silicon atoms in an amorphous (non-crystalline) state on the predetermined location of the non-volatile storage transistor; forming a dielectric layer on the top surface of the first conductive layer; a step of depositing;
depositing a second conductive layer on top of the dielectric layer, the first conductive layer forming a floating r-) and the second conductive layer forming a control date within the predetermined location of the non-volatile storage transistor; Step 5 includes patterning the first and second conductive layers.

According to the present invention, a manufacturing process for two conductive interlayer capacitors in integrated circuit manufacturing is provided, the manufacturing process comprising:
depositing a first conductive layer containing more than 0 silicon atoms in an amorphous (non-crystalline) state; depositing a dielectric layer on top of the first conductive layer; and depositing a second conductive layer on the first conductive layer. depositing a dielectric layer on top.

〔Example〕

The invention will be explained below with reference to the accompanying drawings.

Here, the original F! At--discussed in detail using its preferred embodiment. However, the present invention provides a widely applicable creative idea, and the relationship of the specific components to which it can be translated into embodiments may vary; therefore, it will be discussed. It should be appreciated that the specific examples are merely illustrative of the implementation and application of the invention in some particular manner and are not intended to limit the scope of the invention.

According to the present invention, between the first polycrystalline (poly-1) layer/interlayer dielectric/second polycrystalline (poly-2) layer applied to VLSI fabrication requiring ultra-thin dielectric layers, This shows a process to obtain an extremely smooth interface. The first polycrystalline layer is 560°C
Phosphorus atoms (31
P) Ions are implanted at an energy of 5'0 keV and at a concentration of approximately 1. Implant doped with 1016 Ox/crIL2. This is followed by an interlayer dielectric, i.e. 360× thick
5iO2 (bottom side)/thickness 85mm Si3N4 (top side) (7) LPCVD deposition (at 800° C.) is performed. The next step is an oxidation treatment (60 min) using water vapor of ci, ooo'c, which transforms a part of the nitride thin film layer (Si3N, ) into oxynitride, resulting in a three-layer dielectric Obtain body membranes. During this oxidation step, the underlying first polycrystalline layer is simultaneously annealed to recrystallize the previously deposited amorphous state, while the first polycrystalline layer and the deposited oxidized dielectric The smooth interface of the body thin film layer is still maintained. Thermal oxidation of a portion of the nitride film layer may also be carried out using shorter times (about 30 minutes) in water vapor at 1,000°C, or alternatively using high pressure oxidation (e.g. (approximately 27 minutes in water vapor at 850 °C under atmospheric pressure), thereby minimizing excessive lateral migration of dopane species (such as arsenic resulting from buried diffusion) within the underlying silicon single crystal. It can also be done by converting

Following the formation of the interlayer dielectric thin film layer, a second polycrystalline bilayer is formed.
Deposited under 620°C, then POCl2 at 950°C
The remaining device is then processed using conventional techniques. done and completed.

The method used in one embodiment of the invention is compared below with the method of RCA by Faraone et al.

Processing steps Method of the present invention RCA method Thermal oxidation 850°C steam 750 people The important difference between the above two methods is that the present invention applies the LPCVD method to the upper surface of the n+ type first polycrystalline layer in an amorphous state. Depositing the glabellar dielectric and then depositing the first polycrystalline layer t-i
, o o o o C for recrystallization by annealing, whereas the RCA method grows a thermally oxidized dielectric on top of the n+ type first polycrystalline layer in an amorphous state. be. The deposition of interlayer dielectric thin films provides a more productive and reproducible process than that taught in the Faraon paper, since thermal oxidation provides less control in growing thin film oxides. This is because it is difficult.

The process taught by the present invention applies to EPROM and EEPROM
It is applicable to a wide range of high voltage integrated circuits, including controllers, analog components, etc.

Second polycrystalline layer/interlayer dielectric/
Each interface of the first polycrystalline layer can be seen in a high-resolution cross-sectional transmission electron microscope image (hereinafter referred to as 'rlli4) reproduced in FIG. For comparison, in FIGS. 1 and 2, the results obtained by other treatments are similarly indicated by -.

Of course, these figures demonstrate that the first polycrystalline layer/interlayer dielectric/second polycrystalline layer obtained by the present invention is extremely smooth, much smoother than that obtained by the prior art. clearly shows.

As these TEMs show, IE of 7 Alaon
IIJ Technical Report: Paper published in Electronic Devices (Fig. 9,
According to the teachings of Figure 10), in the case of polycrystalline layers deposited at 620°C (first polycrystalline layer/dielectric) the interface roughness shows approximately 300-500 degrees, while at 560°C If amorphous silicon is used, the interface roughness will be approximately 120~
22oXt- is allowed to give. On the contrary,
The TEM of FIG. 3 shows that by using the present invention, the interface roughness becomes extremely smooth, that is, the excursion
sion) is certainly less than 55 people, and even less than 1C is possible.

FIGS. 4A to 4C show cross sections at each processing step according to the processing order of samples in the manufacture of an EFROM according to the present invention. A substrate 10 (preferably a P-on-P epitaxial structure) has an n+ bit line diffusion region 12, the latter covered by a self-aligned thick oxide (hereinafter 5ATO) region 14. . Thin oxide layer 16 is grown within the five ATO region 140 spacing to become the date oxide of a floating r-) avalanche metal oxide semiconductor (hereinafter referred to as FAMO8) transistor. Now silicon is deposited forming the first polycrystalline level 18, but this layer (at this point)
It is not polycrystalline but amorphous. This layer is implanted to achieve the desired conductivity and then patterned and etched using conventional techniques to produce the structure shown in FIG. 4A.

Next, as shown in FIG. 4B, a dielectric thin film layer 20 is formed.
is completely covered. Dielectric thin film layer 20 is preferably deposited as a multilayer structure, the top layer of which is preferably converted into a composite dielectric layer by a short high temperature oxidation step. As a result, as mentioned above, the oxide/nitride/oxide layer
The structure is obtained. However, as long as the amorphous first polycrystalline layer 18 of silicon is not substantially oxidized, a wide variety of other dielectric thin film structures (single or multilayer, compositions or simple compositions) may be used. Available for use.

Advanced EFR with approximately 1 μm spacing between diffusion regions 12
For OM, the dielectric thickness used is preferably equivalent to an oxide thickness of about 400 mm (as mentioned above), but of course other thicknesses are preferably less than this. short) can also be used instead.

After the dielectric thin film layer 20 is deposited, the structure is preferably subjected to a high temperature anneal, thereby forming the first polycrystalline layer 1.
8 is recrystallized to lower its resistivity. After this stage,
Layer 18 becomes polycrystalline (even if initially amorphous). The dielectric thin film layer 20 is now stripped at its periphery in order to grow the r-) oxide film for the peripheral device. The deposition of the second polycrystalline layer 22 can then proceed, i.e. an etching process in which the second polycrystalline layer 22 is preferably V-shaped by diffusion and then subjected to a patterning and etching process. This is done using a stacked etch process, which removes the second polycrystalline layer 22 (5K, as is well known in EFROM technology), the thin dielectric layer 20 . The first polycrystalline layer 18 is sequentially etched. The processing is
Other conventional steps then proceed, such as interlayer dielectric deposition, contact etch, metal etch, and protective outer coating deposition.

Of course, the second polycrystalline layer does not have to be strictly silicon, and may be a metal or layered structure. Silicide/polycrystalline silicon/silicide sandwich structures are certainly included, and similar deposition and electrical properties may be used in future processes to replace the polycrystalline silicon used in this process. It is intended to include the future structure of the three-dimensional structure. Furthermore, some degree of admixture with other materials is permitted, as long as the first polycrystalline layer is substantially amorphous when deposited and contains a large proportion of silicon.

[Effect] As described above, the present invention provides the interface between layers 18 and 20 and the layer 20.
and 22 are otherwise smooth and have the decisive advantage of being much smoother than was possible in the prior art without introducing significant additional processing complexity.

As will be appreciated by those skilled in the art, the invention is susceptible to a wide range of modifications and variations and is therefore not limited in scope except as specified in the claims below.

Regarding the above description, the following sections are further disclosed.

(1)50. a first polycrystalline conductive layer containing more than % of silicon atoms; a dielectric covering an upper surface of the first conductive layer; and a second conductive layer covering an upper surface of the dielectric; An integrated circuit capacitor characterized in that the interface between the conductive layer and the conductive layer has a maximum local deviation of about 60i perpendicular to the interface.

(2) (a) depositing a first conductive layer in an amorphous (and non-crystalline) state comprising more than 50% silicon atoms; and (b) depositing a dielectric material over the top surface of the first conductive layer. (c) depositing a second conductive layer over the top surface of the dielectric.

(3) an integrated circuit capacitor, comprising: a first polycrystalline conductive layer containing more than 50 silicon atoms; a composite dielectric covering an upper surface of the first conductive layer; and a second conductive layer covering an upper surface of the dielectric; Applying a voltage to the capacitor that corresponds to at least a quarter of the voltage that would be required to breakdown the dielectric if the dielectric were an ideal dielectric having a layer thickness of the dielectric. 1-* The integrated circuit capacitor comprising: a device for applying an electric current;

(4)(c)) Transistor channel region and 0))
(c) a floating date overlying and capacitively coupled to the transistor channel region; and (c) a control date capacitively coupled to the floating date; ) is capacitively coupled to said floating date through a dielectric having a maximum local excursion of 80 perpendicular to the interface.

(5) (a)) Langister field and 0
)) a floating r-t overlying and capacitively coupled to the transistor channel region; and (c) a control r-t capacitively coupled to the floating date.
-), wherein the control date is coupled to the floating date through a dielectric having a maximum local deviation perpendicular to the interface and corresponding to 10 inches of the thickness of the dielectric. sexual memory cell.

(6) The manufacturing method according to item 2, wherein the first conductive layer contains more than 50 silicon atoms.

(7) The manufacturing method according to item 2, wherein the step of depositing the dielectric includes low pressure chemical vapor deposition.

(8) The manufacturing method according to item 2, wherein the step of depositing the dielectric includes a composite dielectric.

9. The method of claim 2, wherein the step of depositing the dielectric includes a layered dielectric comprising multiple layers of distinct components.

σ1 The manufacturing method according to item 2, wherein the step of depositing the first conductive layer is performed at a temperature lower than 600°O.

αυ The method of claim 2, wherein the first conductive layer is deposited to a thickness less than 3.000 amps.

2. The method of claim 2, wherein the dielectric is deposited to a total thickness of less than 500X.

3. The manufacturing method according to claim 2, wherein the first conductive layer is not oxidized at all before the step of depositing the dielectric on the upper surface of the conductive layer.

3. The method of claim 2, wherein the first conductive layer is doped by ion implantation before depositing the dielectric on the top surface of the conductive layer.

(c) forming a date oxidation gt on the predetermined location of the non-volatile storage transistor; (c) silicon atoms exceeding 50% on the predetermined location of the non-volatile storage transistor; (e) depositing a dielectric material over the upper surface of the first conductive layer; depositing a second conductive layer over an upper surface of the body; (f) forming a floating layer in the predetermined location of the nonvolatile storage transistor; said first so as to form a control r-)
A method of manufacturing a nonvolatile memory cell, comprising the steps of patterning a conductive layer and the second conductive layer.

[Brief explanation of the drawing]

FIG. 1 is a photograph of a crystal structure showing a cross section of an integrated circuit capacitor manufactured according to the prior art; FIG. 2 is a photograph of a crystal structure showing a cross section of an integrated circuit capacitor manufactured according to another prior art; FIG. 3 is a photograph of a crystal structure showing a cross section of an integrated circuit capacitor manufactured according to the present invention, and FIGS. 4A to 4C are cross sections of a sample at processing stages corresponding to the processes for manufacturing an EPROM cell according to the present invention. Figure. [Explanation of symbols] 10: Semiconductor substrate 12: N+ bit line diffusion region 14: Self-aligned thick film oxide (5ATO) region 16: Thin film oxide layer 18: First polycrystalline layer 20: Dielectric thin film layer 22: Second polycrystalline layer

Claims (2)

[Claims] (1) The first polycrystalline conductive layer includes a first polycrystalline conductive layer containing more than 50% silicon atoms, a dielectric covering the upper surface of the first conductive layer, and a second conductive layer covering the upper surface of the dielectric; An integrated circuit capacitor characterized in that an interface between the layer and the second conductive layer has a maximum local deviation perpendicular to the interface of about 60 Å. (2) (a) depositing a first conductive layer containing more than 50% silicon atoms in an amorphous (and non-crystalline) state; and (b) depositing a dielectric layer over the top surface of the first conductive layer; A method of manufacturing an integrated circuit capacitor comprising the steps of: depositing a thin film layer; and (c) depositing a second conductive layer over the top surface of the dielectric.