JP2010098657A - Differential amplifier circuit and ring oscillator circuit employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new differential amplifier circuit and ring oscillator circuit suppressing manufacturing processes, power supply voltage and variation in output delay amount with respect to temperature variation without losing differential gains of whole circuit. <P>SOLUTION: Two output terminal charging/discharging circuits are provided which are comprised of constant current sources 34, 35 and discharging transistors 31, 33 and on the basis of differential input signals, output terminals are charged/discharged, thereby producing two output signals obtained by amplifying the input signals. In order to provide differential gains to these two output signals, output nodes of the two output terminal charging/discharging circuits are interconnected to an open drain output type latch circuit 28. Switch circuits 21, 22 are provided in an output unit of the latch circuit 28, ON/OFF control is performed on the switch circuits 21, 22 in accordance with differential input signals so that, when output signals start rising from L level, operation for the latch circuit 28 to maintain the output signals in the L state is forcibly brought to an off-state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit that amplifies a differential input signal and differentially outputs the differential input signal. In particular, the present invention relates to a two-input circuit that is required to reduce variations in output delay time, such as a delay element of a PLL (Phase Locked Loop) ring oscillator. This invention relates to a two-output differential amplifier circuit and a ring oscillator circuit using the same.

In recent years, demands for low power supply voltage operation and high-speed operation are increasing due to scaling rules for miniaturization of manufacturing processes of large-scale integrated circuits.
In response to such demands, the differential circuit can halve the signal amplitude around one circuit compared to a single-ended circuit, which is advantageous for both low power supply voltage operation and high-speed operation. It has been adopted in many applications.

However, there are cases where it is not possible to meet the above-mentioned requirements of the system simply by adopting a differential circuit. Specifically, due to insufficient voltage headroom and bandwidth in the amplification type circuit, low power supply voltage operation and sufficient differential gain during high-speed operation may not be ensured, and the output waveform may become dull or distorted. .
As a countermeasure in such a case, for example, in Patent Document 1 below, even if a differential latch circuit is added to the output portion of the differential circuit, the gain of the differential amplifier circuit that is the main component of the amplification operation is reduced. Have proposed a method in which the differential gain is supplementarily improved by the added differential latch circuit.

FIG. 10 shows an example of a conventional differential amplifier circuit to which this differential latch circuit is added.
In the figure, reference numeral 1 is a power supply voltage (hereinafter referred to as “Vdd”), 2 is a ground voltage (hereinafter referred to as “Vss”), 3 and 4 are PMOS transistors whose source terminals are connected to Vdd1, respectively, as active load resistors. Function. Reference numerals 21 to 28 denote NMOS transistors. Symbols a and b are input terminals to which input signals are input, c and d are output terminals from which logic signals are output, and symbols A and B are nodes to which output terminals c and d are connected, respectively.

The node A is connected to the drain terminals of the PMOS transistor 3 and NMOS transistors 21 and 25, and the gate electrode of the NMOS transistor 26, respectively, while the node B is connected to the drain terminals of the PMOS transistor 4, the NMOS transistors 22 and 26, and The gate electrodes of the NMOS transistors 25 are connected to each other.
Symbol C indicates a node to which the NMOS transistors 23, 24 and 27 are connected in common. On the other hand, the source terminals of the NMOS transistors 25 and 26 are commonly connected to the drain terminal of the NMOS transistor 28.

A symbol D indicates a node to which the NMOS transistors 25, 26 and 28 are connected in common. Further, the source terminals of the NMOS transistors 27 and 28 are commonly connected to Vss2. The input terminals a and b are connected to the gate electrodes of the NMOS transistors 23 and 24, respectively.
Vin1 and Vin2 indicate the potentials of the input signals applied to the input terminals a and b, respectively. Vout1 and Vout2 indicate the potentials of the output signals output from the output terminals c and d, respectively.

Bias1 is a bias voltage applied to the gate electrode for operating the NMOS transistor 27 as a constant current source in the saturation region, and Bias2 is a gate electrode for operating the PMOS transistors 3 and 4 in the saturation region using the active load resistor. Is a bias voltage commonly applied to the.
X is a digital signal applied to the gate electrodes of the NMOS transistors 21 and 22, and / X is a digital signal applied to the gate electrode of the NMOS transistor 28. X and / X are digital signals complementary to each other, and controls switching between the through mode and the latch mode in the differential amplifier circuit.
The NMOS transistors 21, 22 and 28 function as switches, and control signals X and / X are applied so as to operate in a linear region in the ON state. Usually, the voltage of Vdd1 is used as the H level.

Next, the operation of the differential amplifier circuit having such a configuration will be described.
An analog signal voltage is always applied to the input terminals a and b. In this circuit, when X = H and / X = L, the through mode is set, and when X = L and / X = H, the latch mode is set. The two modes are alternately repeated at predetermined time intervals.

(1) When X = H and / X = L (through mode)
The NMOS transistors 21 and 22 are turned on, and the NMOS transistor 28 is turned off. At this time, the current generated by the NMOS transistor 27 which is a current source flows between Vdd1 and the node C, and the NMOS transistors 23, 24 and 27 and the PMOS transistors 3 and 4 constitute a differential amplifier circuit. The
Therefore, the output signals amplified to the potential difference between the output potentials Vout1 and Vout2 with respect to the potential difference between the input voltages Vin1 and Vin2 are output from the terminals c and d. On the other hand, since the node D is not conducted to Vss2, the latch operation does not function in the NMOS transistors 25 and 26.

(2) When X = L and / X = H (latch mode)
Conversely, the NMOS transistors 21 and 22 are turned off, and the NMOS transistor 28 is turned on. At this time, the node D is made conductive to Vss2, and the NMOS transistors 25 and 26 form a latch circuit. On the other hand, since no current flows from Vdd1 to the node C, differential amplification with respect to the input voltages Vin1 and Vin2 does not function.
First, when Vin1> Vin2 in the through mode immediately before the start of the latch mode, Vout1 <Vout2, and the potential difference between Vin1 and Vin2 is amplified. When switching to the latch mode, Vout1 becomes the gate voltage of the NMOS transistor 26 and Vout2 becomes the gate voltage of the NMOS transistor 25. Therefore, the drain current of the NMOS transistor 25 becomes larger than the drain current of the NMOS transistor 26.

As a result, the drain potential Vout1 of the NMOS transistor 25 is further reduced, while the drain potential Vout2 of the NMOS transistor 26 is further increased. Vout1 = L and Vout2 = H are determined by an interaction in which an increase in Vout2 promotes a decrease in Vout1, and conversely, a decrease in Vout1 promotes an increase in Vout2. In this way, digital signals are output from the output terminals c and d.
JP-A-8-33586

However, the conventional differential amplifier circuit as shown in FIG. 10 has the following two technical problems.
The first problem is a shortage of voltage headroom.
The NMOS transistors 21 and 22 that operate as switches are provided between the drain terminals of the NMOS transistors 23 and 24 that receive the input signal and the nodes A and B at which the output signal appears, respectively. However, when the NMOS transistors 21 and 22 are in the ON state (that is, in the through mode), the voltage applied to the drain terminals of the NMOS transistors 23 and 24 decreases due to the voltage drop generated in the NMOS transistors 21 and 22.

  In order to perform a differential amplification operation with a sufficient differential gain, it is desirable that both NMOS transistors 23 and 24 that receive an input signal operate in a saturation region when Vin1 = Vin2. However, in the situation where the voltage at the drain terminal is reduced as described above, the potential difference between the drain and the source is reduced, so that the NMOS transistors 23 and 24 operate in a linear region, resulting in a reduction in differential gain.

Furthermore, the voltage applied to the drain terminal of the NMOS transistor 27 also decreases due to the voltage drop caused by the NMOS transistors 23 and 24 operating in the linear region. As a result, the constant current property of the transistor 27 that should function as a constant current source may be impaired, and the differential gain of the entire differential amplifier circuit may be reduced and the output delay amount may be increased. Therefore, there is a possibility that differential amplification with a good gain cannot be performed for the two signal inputs Vin1 and Vin2.
As a result, even if the signals amplified by the differential amplifiers 12 and 13 as shown in FIG. 11 are input to the differential amplifier circuit of FIG. 10, the differential amplifier circuit cannot amplify to a predetermined value in the through mode. When shifting to the latch mode, the latch operation may not be performed accurately and quickly.

The second problem is the generation of delay due to the fluctuation of the output level at the time of mode switching.
In order to switch between the through mode and the latch mode, with respect to the control signals X and / X, the states X = H, / X = L (through mode), and X = L, / X = H (latch mode) The power supply voltage is Vdd1, the output current amount of the constant current source 27 is I0, the ON resistance value of the PMOS transistors 3 and 4 is R0, and the NMOS transistors 25 and 26 are determined to be in the ON state. The ON resistance value at that time is R1. The output H level Vh0 in the through mode is expressed by the following expression (1).
Vh0 = Vdd1 (1)

On the other hand, since the output H level Vh1 in the latch mode is generated by dividing the power supply voltage by the resistors R0 and R1, it is expressed by the following equation (2).
Vh1 = R1 × Vdd1 / (R0 + R1) (2)
In the above equation, it is assumed that the PMOS transistors 3 and 4 are operating in the linear region.
Similarly, the output L level V10 in the through mode is expressed by the following equation (3):
V10 = Vdd1-R0 × I0 (3)
The output L level Vl1 in the latch mode is expressed as the ground level Vl1 = 0.
As described above, the latch mode and the through mode are expressed by completely different expressions for the H level and the L level. Therefore, at the moment when the through mode and the latch mode are switched, the output level varies as shown in the timing chart of FIG. Happens.

When it takes time to change the output level, the output delay time increases. That is, the second problem is that extra delay may occur when mode transition between the through mode and the latch mode is performed.
Both the first and second problems result in a large variation in the output delay amount of the circuit with respect to variations in the manufacturing process, power supply voltage, and temperature.
Accordingly, the present invention has been made to solve the above-described problems, and its purpose is to suppress fluctuations in the output delay amount with respect to fluctuations in the manufacturing process, power supply voltage, and temperature without impairing the differential gain of the entire circuit. Another novel differential amplifier circuit and a ring oscillator circuit using the same are provided.

In order to solve the above problems, a differential amplifier circuit according to a first invention is
Including first and second transistors, first and second constant current sources, a latch circuit, and first and second switch circuits;
The first transistor has a drain terminal connected to a first output node which is a connection node of the first output terminal, a source terminal connected to the first power supply terminal, and a gate terminal connected to the first input terminal. The second transistor has a drain terminal connected to a second output node which is a connection node of the second output terminal, a source terminal connected to the first power supply terminal, and a gate terminal The first constant current source is connected to a second input terminal, the drain terminal is connected to the first output node, the source terminal is connected to the second power supply terminal, and the second constant current source is connected to the second input terminal. The constant current source has a drain terminal connected to the second output node and a source terminal connected to the second power supply terminal, and the latch circuit includes the first output node and the second output node. The signal from the node Then, an L level signal and a Hi-Z signal with the first power supply terminal as the ground level are generated from these signal voltages, and are held at the first and second output terminals. The first switch circuit is connected between the first output terminal and the latch circuit, a control terminal is connected to the first input terminal, and the second switch circuit is The control circuit is connected between the second output terminal and the latch circuit, and a control terminal is connected to the second input terminal.

The second invention is
In the differential amplifier circuit according to the first aspect of the present invention, the first switch circuit is deenergized at the same time as the deenergization state of the first transistor is started, and the second switch circuit is decoupled from the second transistor. The differential amplifier circuit is characterized in that it is de-energized at the same time as the de-energized state starts.

The third invention is
In the differential amplifier circuit according to the first or second invention, the first constant current source includes a third transistor having a source terminal connected to the second power supply terminal and a constant voltage applied to the gate terminal. And a fourth transistor having a source terminal connected to the drain terminal of the third transistor, a drain terminal connected to the first output node, and a constant voltage applied to the gate terminal,
The second constant current source includes a fifth transistor having a source terminal connected to the second power supply terminal, a gate terminal applied with the same constant voltage as the gate terminal of the third transistor, and a source terminal A sixth transistor having a drain terminal connected to the fifth transistor, a drain terminal connected to the second output node, and a gate terminal applied with the same constant voltage as the gate terminal of the fourth transistor; This is a differential amplifier circuit.

The fourth invention is:
In the differential amplifier circuit according to the third invention, the drain areas of the fourth transistor and the sixth transistor are smaller than the drain areas of the third transistor and the fifth transistor. It is a differential amplifier circuit.
The fifth invention is:
In the differential amplifier circuit according to any one of the first to fourth inventions, the latch circuit includes two transistors, and one transistor has a drain terminal connected to the first switch circuit and a source terminal connected to the first switch circuit. The first power supply terminal is connected, the gate terminal is connected to the second output node, the other transistor has a drain terminal connected to the second switch circuit, and a source terminal connected to the first output node. The differential amplifier circuit is connected to a power supply terminal and a gate terminal is connected to the first output node.

The sixth invention is:
In the differential amplifier circuit according to any one of the first to fifth inventions, each of the first and second switch circuits includes a transistor, and a drain terminal of the transistor of the first switch circuit has the first terminal. Are connected to the output node, the source terminal is connected to the latch circuit, the gate terminal is connected to the first input terminal, and the transistor of the second switch circuit has the drain terminal connected to the second output terminal. A differential amplifier circuit comprising: a node; a source terminal connected to the latch circuit; and a gate terminal connected to the second input terminal.

The seventh invention
The differential amplifier circuit according to any one of the first to sixth inventions further includes a buffer circuit, and the buffer circuit has an input terminal that is a control terminal of the first transistor and a control terminal of the second transistor. The differential amplifier circuit is characterized in that the output terminal is connected to the first switch circuit and the second switch circuit.

The eighth invention
The differential amplifier circuit according to any one of the first to sixth inventions further includes a buffer circuit, and the buffer circuit has an input terminal connected to the first switch circuit and the second switch circuit, An output terminal is connected to a control terminal of the first transistor and a control terminal of the second transistor.
The ninth invention
In the differential amplifier circuit according to any one of the first to eighth inventions, a common connection point between the source terminal of the first transistor and the source terminal of the second transistor, the first power supply terminal, The differential amplifier circuit is characterized in that they are directly connected to each other.

The tenth invention is
In the differential amplifier circuit according to any one of the first to eighth inventions, a common connection point between the source terminal of the first transistor and the source terminal of the second transistor, the first power supply terminal, A differential amplifier circuit comprising a constant current source between the two.
The ring oscillator circuit according to the eleventh invention is
A plurality of differential amplifier circuits according to any one of the first to tenth inventions are provided, and the oscillation frequency is controlled by setting the amount of current flowing through each differential amplifier circuit.

  In the differential amplifier circuit of the present invention, the first output node and the drain terminal of the first transistor are directly connected, and the second output node and the drain terminal of the second transistor are directly connected. The switch circuit is not sandwiched between them. Further, since the first transistor and the second transistor are used as switches for discharging the output node, the operation in the linear region is also possible. As a result, it is possible to prevent performance degradation due to a decrease in voltage headroom.

  Further, in the differential amplifier circuit of the present invention, when the H level is output to the first output node, only one state is assumed in which the first transistor is in the off state and the first switch circuit is also in the off state, and the output level is also high. Determined uniquely. Further, at the time of L level output, the first switch circuit is on and the first switch circuit is only on, and the output level is uniquely determined. Similarly, the output level is uniquely determined for the second output node.

Thereby, the output node does not take different levels due to different modes such as the through mode and the latch mode. That is, there is no new output delay due to the fluctuation of the output H / L level every time the mode is switched.
Further, the fourth transistor and the sixth transistor having a small drain area add the drain capacitances of the fifth transistor and the sixth transistor acting as constant current sources to the first output node and the second output node. Therefore, high-speed operation is possible.
Also, by connecting a plurality of differential amplifier circuits of the present invention as delay elements in a ring shape, it is possible to obtain a high-quality ring oscillator circuit that reduces oscillation frequency variations even during manufacturing process, power supply voltage, and temperature fluctuations. it can.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit configuration diagram showing a first embodiment of a differential amplifier circuit 100 according to the present invention.
In the figure, reference numeral 1 is a power supply voltage (Vdd), 2 is a ground voltage (Vss), and 34 and 35 are PMOS transistors each having a source terminal connected to Vdd1 and function as a constant current source. Reference numerals 31, 33, 21, 22, 25, and 26 are NMOS transistors. Symbols a and b are input terminals to which input signals are input, c and d are output terminals from which logic signals are output, and A and B are nodes to which output terminals c and d are connected, respectively.

The node A is connected to the drain terminals of the PMOS transistor 34 and the NMOS transistor 31 and the gate terminal of the NMOS transistor 26.
On the other hand, to the node B, the drain terminals of the PMOS transistor 35 and the NMOS transistor 33 and the gate terminal of the NMOS transistor 25 are connected.
The NMOS transistor 21 has its source terminal connected to the drain terminal of the NMOS transistor 25, while the NMOS transistor 22 has its source terminal connected to the drain terminal of the NMOS transistor 26.

Further, the source terminals of the NMOS transistors 25, 26, 31, and 33 are all connected to Vss2.
The NMOS transistors 25 and 26 constitute an open drain output type latch circuit 28.
Vin1 and Vin2 indicate the potentials of the input signals applied to the input terminals a and b, respectively. Vout1 and Vout2 indicate the potentials of the output signals output from the output terminals c and d, respectively.

Bias3 is a bias voltage given to operate the PMOS transistors 34 and 35 as a constant current source.
Then, Vin1 is applied to the gate terminal of the NMOS transistor 21, and Vin2 is applied to the gate terminal of the NMOS transistor 22.
Since the inputs Vin1 and Vin2 are complementary signals, the NMOS transistors 21 and 22 perform control to turn off only one of the two outputs of the latch circuit 28 and turn on the other.

Next, the operation of the differential amplifier circuit 100 will be described with reference to the timing chart of FIG.
First, the operation of the amplification stage constituted by the NMOS transistors 31 and 33 and the PMOS transistors 34 and 35 will be described as a first point.
As shown in the figure, differential signals Vin1 and Vin2 having complementary logic are input to input terminals a and b connected to the NMOS transistors 31 and 33, respectively. The threshold value of the NMOS transistors 31 and 33 receiving this is set to Vth.
As for the NMOS transistor 31 that receives Vin1, when Vin1 ≧ Vth, the NMOS transistor 31 is turned on, and the output terminal c is discharged to make Vout1 transition toward the L level.

Further, when Vin1 <Vth, the NMOS transistor 31 is turned off, and the output terminal c is charged by the PMOS transistor 34 serving as a constant current source, whereby Vout1 is shifted toward the H level.
Further, the same behavior is obtained with respect to changes in Vin2 and Vout2.
That is, for the NMOS transistor 33 that receives Vin2, when Vin2 ≧ Vth, the NMOS transistor 33 is turned on, and the output terminal d is discharged to make Vout2 transition toward the L level.
Further, when Vin2 <Vth, the NMOS transistor 33 is turned off, and the output terminal d is charged by the PMOS transistor 35 serving as a constant current source, whereby Vout2 is shifted toward the L level.

Since Vin1 and Vin2 have a differential relationship, Vout1 and Vout2 have a differential relationship from the above operation.
The reason why the Vout1 rising start timing and the Vout2 falling timing are slightly shifted in FIG. 2 is that the timing across the threshold value Vth of the NMOS transistors 33 and 35 is shifted between the input signals Vin1 and Vin2. . This timing shift can be ignored if the input signals Vin1 and Vin2 are steep enough.

Next, the operation of the latch circuit 28 and the NMOS transistors 21 and 22 serving as output switches thereof will be described at the second point.
Vin1 is input to the gate terminal of the NMOS transistor 21, and Vin2 is input to the gate terminal of the NMOS transistor 22. The on / off control of the NMOS transistors 21 and 22 is the same as that of the NMOS transistors 31 and 33. That is, when Vin1 ≧ Vth, the NMOS transistor 21 is turned on, and conducts between the output latch circuit 28 and the output terminal c.

When Vin1 <Vth, the NMOS transistor 21 is turned off to make the output latch circuit 28 and the output terminal c non-conductive.
On the other hand, when Vin2 ≧ Vth, the NMOS transistor 22 is turned on and conducts between the output latch circuit 28 and the output terminal d.
Further, when Vin2 <Vth, the NMOS transistor 22 is turned off, and the output latch circuit 28 and the output terminal d are made non-conductive.

Here, the NMOS transistor 21 is always turned off when the NMOS transistor 31 is turned off, that is, when Vout1 is transitioned to H.
As a result, the charging current output for the constant current source PMOS transistor 34 to increase the potential Vout1 is prevented from escaping to the latch circuit side.
Similarly, the NMOS transistor 22 is always turned off when the NMOS transistor 33 is turned off, that is, when Vout2 is changed to H.
As a result, the charging current output for the constant current source PMOS transistor 35 to increase the potential Vout2 is prevented from escaping to the latch circuit side.

Next, the principle that the open drain output type latch circuit 28 gives the differential gain to the differential amplifier circuit 100 of the present invention at the third point will be described with reference to the timing chart of FIG.
In order to explain the principle of generating the differential gain, it is assumed that the output signals Vout1 and Vout2 have a slight difference and that Vout1 is stopped at a potential higher than Vout2 (state before time t1 in FIG. 3). To do.
In addition, the potentials of Vout1 and Vout2 at this time are higher than the threshold value Vth of the NMOS transistors 25 and 26 included in the latch circuit 28.

  Since Vout1> Vout2, the gate terminal potential of the NMOS transistor 26 is higher than the gate terminal potential of the NMOS transistor 25. That is, the current that the NMOS transistor 26 draws from the output terminal c is larger than the current that the NMOS transistor 25 draws from the output terminal d. Therefore, as shown between times t1 and t2 in FIG. 3, the slope of decreasing the potential of Vout2 is steeper than the slope of decreasing the potential of Vout1.

After the time t2 when Vout2 crosses Vth, the NMOS transistor 25 is completely turned off, so that the decrease in the potential of Vout1 is completed and thereafter the potential does not change.
On the other hand, since the NMOS transistor 26 remains on after time t2, the potential of Vout2 drops to the ground level. After time t3 when the ground level is reached, Vout2 is constant at the ground level.

In this way, a minute potential difference between Vout1 and Vout2 before time t1 is greatly widened after time t3. That is, this latch circuit has a function of improving the differential gain of the differential amplifier circuit 100 of the present invention.
In the above description, the switch circuits 21 and 22 are omitted for simplicity. However, when the operation is reconsidered with a circuit including the switch circuits 21 and 22, in the state of FIG. 3, the switch 22 on the Vout2 side that is dropped to L is turned on. In the state, the switch 21 on the Vout1 side is turned off.

  Accordingly, the operation of Vout2 in FIG. 3 is not changed, and on the other hand, the Vout1 potential does not decrease on the Vout1 side because the switch 21 is turned off. That is, the decrease in the potential Vout1 seen from time t1 to time t2 is eliminated, and the potential difference between Vout1 and Vout2 increases more and more. That is, even if the switch circuits 21 and 22 are included, the differential amplifier circuit 100 of the present invention has a differential gain.

Next, the difference between the differential amplifier circuit 100 of the present invention configured as described above and the prior art as shown in FIG. 10 will be described.
As shown in FIG. 1, in the differential amplifier circuit 100 of the present invention, the drain terminals of NMOS transistors 21 and 22 that receive input signals Vin1 and Vin2 are directly connected to output terminals c and d. As in the example, the switch circuit is not sandwiched between the output terminals c and d like the NMOS transistors 23 and 24.
Furthermore, since the differential amplifier circuit 100 of the present invention is used as a switch for the NMOS transistors 21 and 22 to discharge the output node, it can operate in a linear region.
As a result, the differential amplifier circuit 100 of the present invention can avoid performance degradation due to voltage headroom reduction that may occur in the conventional example.

  Further, the differential amplifier circuit 100 according to the present invention takes only one state in which the NMOS transistor 31 is in the off state and the NMOS transistor 21 is in the off state when the H level is output to the output node A, and the output level is uniquely determined. At the time of L level output, only one state is assumed, in which the NMOS transistor 31 is on and the NMOS transistor 21 is on, and the output level is also uniquely determined. Further, the L level and the H level of the output node B are determined uniquely in the same manner.

Thus, the output node does not take different levels due to different modes such as the through mode and the latch mode that can occur in the conventional example. That is, every time the mode is switched, a new output delay does not occur due to the fluctuation of the output H / L level.
In the differential amplifier circuit 100 of the present invention, a constant current source may be sandwiched between the common source terminal of the NMOS transistors 31 and 33 and Vss2. However, when the constant current source is not used, the NMOS transistors 31 and 33 are used. The response delay of the differential pair composed of the constant current source can be eliminated.

  The response delay of the differential pair here is caused by the delay of the response of the common source node of the differential pair transistor. Regarding the input signals Vin1 and Vin2 applied to the gate terminals of the transistors 31 and 33, Vin1> Vin2 in the initial state, and all constant currents flow to the NMOS transistor 31. Thereafter, at the moment when the differential inputs Vin1 and Vin2 cross and Vin1 = Vin2, only half of the constant current flows to the NMOS transistor 31 and the remaining half flows to the NMOS transistor 31. That is, compared to when Vin1> Vin2, when Vin1 = Vin2, the current amount of the NMOS transistor 33 is halved, so the overdrive voltage is reduced by (1 / √2) times. Along with this, the voltage of the node (referred to as node C) which is the common source node of the NMOS transistors 31 and 33 tends to increase only at the moment of Vin1 = Vin2.

  However, the source terminal capacitance of the NMOS transistors 31 and 33 and the drain capacitance of the constant current source act as loads, so that the voltage rise timing of the node C is delayed from the timing of Vin1 = Vin2. As a result, the opening of the gate-source potential of the differential pair NMOS transistor 31 is delayed, and the NMOS transistor 31 is delayed from being turned on. That is, the output delay of the amplifier circuit, which delays the falling of the output Vout1, is increased. When the constant current source is eliminated as described above, this response delay can be eliminated.

The differential amplifier circuit 100 of the present invention can also be configured by replacing Vdd (power supply), Vss (ground), NMOS transistor, and PMOS transistor.
Further, in the present embodiment, all are constituted by MOS transistors, but may be constituted by bipolar transistors. Also, the source terminal corresponds to the emitter terminal, the drain terminal corresponds to the collector terminal, the gate terminal corresponds to the base terminal, a PNP bipolar transistor is used instead of the PMOS transistor, and an NPN bipolar transistor is used instead of the NMOS transistor. Also good.

(Second Embodiment)
Next, FIG. 4 is a circuit configuration diagram showing a second embodiment of the differential amplifier circuit 100 according to the present invention.
In the figure, reference numeral 1 is a power supply voltage (Vdd), 2 is a ground voltage (Vcc), and 34 and 35 are PMOS transistors each having a source terminal connected to Vdd1 and function as a constant current source. PMOS transistors 36 and 37 are cascode-connected to the drain terminals of the PMOS transistors 34 and 35. Reference numerals 21, 22, 25, 26, 31, and 33 denote NMOS transistors. Further, a and b are input terminals to which input signals are input, c and d are output terminals from which logic signals are output, and A and B are nodes to which the output terminals c and d are connected, respectively. The other symbols or symbols indicate the same or corresponding ones as in the first embodiment (FIG. 1).

The basic operation of the differential amplifier circuit 100 according to the present embodiment configured as described above is the same as that in the first embodiment, but in the first embodiment, the output nodes A and B Since the constant current source PMOS transistors 34 and 35 are directly connected to each other, the drain capacitance of the PMOS transistors 34 and 35 may be directly added to the output node, which may increase the output delay.
Therefore, in this embodiment, cascode PMOS transistors 36 and 37 having a small drain area are inserted between the PMOS transistors 34 and 35 and the output node.

Since the PMOS transistors 36 and 37 operate in the saturation region, the load capacitance on the source terminal side becomes invisible from the drain terminal due to the pinch-off phenomenon. For this reason, the load capacitances of the output nodes A and B that are attributable to the PMOS transistor are only 36 and 37 having a small drain capacitance, and can operate at a higher speed than the configuration of the first embodiment.
Since the PMOS transistors 36 and 37 lower the voltage between the drain and source terminals of the PMOS transistors 34 and 35, the configuration of this embodiment can be used only when the voltage headroom of the PMOS transistors 34 and 35 has a margin. .

(Third embodiment)
Next, FIG. 5 is a circuit configuration diagram showing a third embodiment of the differential amplifier circuit 100 according to the present invention.
Similar to the above embodiment, reference numeral 1 is a power supply voltage (Vdd), 2 is a ground voltage (Vcc), and 34 and 35 are PMOS transistors whose source terminals are connected to Vdd1, respectively, and function as constant current sources. Reference numerals 31, 33, 21, 22, 25, and 26 are NMOS transistors. Further, a and b are input terminals to which input signals are input, c and d are output terminals from which logic signals are output, and A and B are nodes to which the output terminals c and d are connected, respectively. Other symbols or symbols are the same as or equivalent to those in FIG.

The differential amplifier circuit 100 according to the present embodiment further includes an ethical buffer circuit 38. That is, the buffer circuit 38 has an input terminal connected to the control terminals of the NMOS transistors 31 and 33 and an output terminal connected to the NMOS transistors 21 and 22, respectively.
The basic operation of the differential amplifier circuit 100 according to the present embodiment configured as described above is the same as that in the first embodiment, but in the first embodiment, the input signals Vin1 and Vin2 are the same. When the transition of the output voltage is slow, the levels of the outputs Vout1 and Vout2 become H level and H level, or L level and L level, which may make the differential logic undefined.

FIG. 6 is an example of a timing chart for explaining this behavior.
In the example of FIG. 6, since the cross-point potential of the inputs Vin1 and Vin2 is higher than the threshold value Vth of the NMOS transistors 31 and 33, a period in which both the NMOS transistors 31 and 33 are in the ON state occurs. Furthermore, since the transitions of the inputs Vin1 and Vin2 are gentle, the period during which both the NMOS transistors 31 and 33 are in the ON state is lengthened. Therefore, the period during which the output nodes A and B are discharged becomes long, and a period in which both the output nodes A and B are at the L level occurs.

By making the transition of the inputs Vin1 and Vin2 sufficiently steep, the period during which both outputs become L as described above becomes sufficiently short, and the influence can be ignored. As one of means for that purpose, there is a method of reducing the load capacity of the input terminal.
In the present embodiment, as described above, the logic buffer circuit 38 is inserted between the input terminal a and the gate terminal of the NMOS transistor 21 and between the input terminal b and the NMOS transistor 22.
As a result, the gate capacitance of the NMOS transistors 21 and 22 among the load capacitances of the input terminals a and b can be reduced, and the transitions of the inputs Vin1 and Vin2 can be made steep.

(Fourth embodiment)
FIG. 7 is a circuit diagram showing a fourth embodiment of the differential amplifier circuit 100 according to the present invention.
Similar to the above embodiment, reference numeral 1 is a power supply voltage (Vdd), 2 is a ground voltage (Vcc), and 34 and 35 are PMOS transistors whose source terminals are connected to Vdd1, respectively, and function as constant current sources. Reference numerals 31, 33, 21, 22, 25, and 26 are NMOS transistors. Further, a and b are input terminals to which input signals are input, c and d are output terminals from which logic signals are output, and A and B are nodes to which the output terminals c and d are connected, respectively. Other symbols or symbols are the same as or equivalent to those in FIG.

  In the differential amplifier circuit 100 according to the present embodiment, the ethics buffer circuit 38 is further provided as in the third embodiment, but the third embodiment is described. Unlike the buffer circuit 38, the output terminal is connected to the control terminals of the NMOS transistors 31 and 33, and the input terminal is connected to the NMOS transistors 21 and 22, respectively.

The basic operation of the differential amplifier circuit 100 is the same as that of the third embodiment. In the third embodiment, the gate capacitance of the NMOS transistors 21 and 22 is reduced in order to reduce the load capacitance of the input terminal, but the gate capacitance of the NMOS transistors 31 and 33 may be reduced instead. it can.
In this embodiment, since the logic buffer circuit 38 is inserted between the input terminal a and the gate terminal of the NMOS transistor 31 and between the input terminal b and the NMOS transistor 33, the input terminals a and b The gate capacitance of the NMOS transistors 31 and 33 can be reduced, and the transition of the inputs Vin1 and Vin2 can be made steep.

(Fifth embodiment)
Next, FIG. 8 shows a fifth embodiment of a differential amplifier circuit 100 according to the present invention, and shows a novel ring oscillator circuit 200 using a plurality of differential amplifier circuits 100. .
As shown in the figure, this ring oscillator circuit 200 has a configuration in which the above-described differential amplifier circuit 100 according to the present invention is prepared in N stages, and each differential amplifier circuit 100 is cascade-connected in a ring shape. The basic operation of each differential amplifier circuit 100 is as described above.

In particular, when a differential amplifier circuit that does not use a differential pair in which two transistors are paired is used, in the ring oscillator circuit 200 configured as described above, each of the differential amplifier circuits 100 includes a conventional amplifier. The output delay due to the differential pair transistor is also reduced. Thereby, the oscillation frequency variation of the entire ring oscillator can also be improved.
FIG. 9 shows the differential output of each differential amplifier circuit according to the prior art (FIG. 9A) and the present invention (FIG. 9B) when the number of stages of differential amplifier circuits is N = 3. It is the timing chart shown. Is

In FIG. 9A, τ and Δτ represent the output delay amount of each differential amplifier circuit. Δτ represents the output delay due to the differential pair transistor, and τ represents the output delay due to other factors.
In FIG. 9B, τ represents the total delay amount in one differential amplifier circuit.
In FIG. 9A, the oscillation frequency fosc of the ring oscillator is expressed by the following equation (4).
fosc = 6 / (τ + Δτ) (4)

This Δτ varies depending on the manufacturing process, the power supply voltage, and the temperature, so that the oscillation frequency of the ring oscillator varies.
On the other hand, in FIG. 9B, the oscillation frequency fosc of the ring oscillator is expressed by the following equation (5) and does not include output delay due to the differential pair.
fosc = 6 / τ (5)
Therefore, according to the ring oscillator circuit 200 of the present invention, fluctuations in the oscillation frequency of the ring oscillator can be reduced compared with the prior art even if the manufacturing process, power supply voltage, and temperature fluctuate.

1 is a circuit configuration diagram showing a first embodiment of a differential amplifier circuit 100 according to the present invention. FIG. 3 is a timing chart showing the affection of each circuit and the potential of an output signal with respect to time of the differential amplifier circuit 100 according to the first embodiment. It is a timing chart figure showing that differential amplifier circuit 100 concerning a 1st embodiment has differential gain. FIG. 3 is a circuit configuration diagram showing a second embodiment of a differential amplifier circuit 100 according to the present invention. It is a circuit block diagram which shows 3rd Embodiment of the differential amplifier circuit 100 which concerns on this invention. FIG. 6 is a timing chart illustrating the behavior of an output signal when a transition of an input differential signal is gentle in the differential amplifier circuit 100 according to the first embodiment. It is a circuit block diagram which shows 4th Embodiment of the differential amplifier circuit 100 which concerns on this invention. 1 is a circuit configuration diagram showing a ring oscillator circuit 200 formed by cascading a plurality of differential amplifier circuits 100 according to the present invention in a ring shape. FIG. (A) is a timing chart when the response delay of the differential pair is considered in the conventional ring oscillator circuit operation. (B) is a timing chart for explaining the circuit operation of the ring oscillator circuit 200 according to the present invention. It is a circuit block diagram which shows an example of the conventional differential amplifier circuit. It is a circuit diagram of a conventional voltage comparator using a differential latch circuit. FIG. 6 is a timing chart illustrating output operating point fluctuations when the differential amplifier circuit is switched in mode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Differential amplifier circuit 200 ... Ring oscillator circuit 1 ... Power supply voltage (Vdd)
2 ... Ground voltage (Vss)
21, 22 ... NMOS transistors (switch circuits)
25, 26 ... NMOS transistor 28 ... Latch circuit 31, 33 ... NMOS transistor (first and second transistors)
34, 35 ... PMOS transistors (first and second constant current sources (third and fourth transistors))
36, 37 ... PMOS transistors (fourth and sixth transistors)
38 ... Buffer circuit A, B ... Output node a, b ... Input terminal c, d ... Output terminal

Claims (11)

Including first and second transistors, first and second constant current sources, a latch circuit, and first and second switch circuits;
The first transistor is
The drain terminal is connected to a first output node that is a connection node of the first output terminal, the source terminal is connected to the first power supply terminal, and the gate terminal is connected to the first input terminal,
The second transistor is
A drain terminal connected to a second output node which is a connection node of the second output terminal, a source terminal connected to the first power supply terminal, and a gate terminal connected to the second input terminal;
The first constant current source is
A drain terminal connected to the first output node, a source terminal connected to a second power supply terminal,
The second constant current source is
A drain terminal connected to the second output node, a source terminal connected to the second power supply terminal,
The latch circuit is
Signals from the first output node and the second output node are input, and an L level signal and a Hi-Z signal with the first power supply terminal as a ground level are generated from the signal voltages. It is an open drain output type that is held at the first and second output terminals,
The first switch circuit includes:
Connected between the first output terminal and the latch circuit, and a control terminal is connected to the first input terminal;
The second switch circuit includes:
A differential amplifier circuit, wherein the differential amplifier circuit is connected between the second output terminal and the latch circuit, and a control terminal is connected to the second input terminal. The differential amplifier circuit according to claim 1,
The first switch circuit is de-energized at the same time as the de-energization state of the first transistor starts,
The differential amplifier circuit, wherein the second switch circuit is de-energized at the same time as the de-energization state of the second transistor is started. The differential amplifier circuit according to claim 1 or 2,
The first constant current source is
A third terminal having a source terminal connected to the second power supply terminal, a constant voltage applied to the gate terminal, a source terminal connected to the drain terminal of the third transistor, and a drain terminal connected to the first transistor A fourth transistor connected to the output node and having a constant voltage applied to the gate terminal;
The second constant current source is
A fifth transistor having a source terminal connected to the second power supply terminal, a gate terminal applied with the same constant voltage as the gate terminal of the third transistor, and a source terminal connected to the drain terminal of the fifth transistor; And a sixth transistor having a drain terminal connected to the second output node and a gate terminal applied with the same constant voltage as the gate terminal of the fourth transistor. circuit. The differential amplifier circuit according to claim 3,
The differential amplifier circuit, wherein drain areas of the fourth transistor and the sixth transistor are smaller than drain areas of the third transistor and the fifth transistor. The differential amplifier circuit according to any one of claims 1 to 4,
The latch circuit is composed of two transistors,
One transistor is
A drain terminal connected to the first switch circuit, a source terminal connected to the first power supply terminal, a gate terminal connected to the second output node;
The other transistor is
A differential amplifier circuit, wherein a drain terminal is connected to the second switch circuit, a source terminal is connected to the first power supply terminal, and a gate terminal is connected to the first output node. The differential amplifier circuit according to any one of claims 1 to 5,
The first and second switch circuits are each composed of a transistor,
The transistor of the first switch circuit is
A drain terminal connected to the first output node, a source terminal connected to the latch circuit, a gate terminal connected to the first input terminal;
The transistor of the second switch circuit is
A differential amplifier circuit characterized in that a drain terminal is connected to the second output node, a source terminal is connected to the latch circuit, and a gate terminal is connected to the second input terminal. The differential amplifier circuit according to any one of claims 1 to 6,
Furthermore, a buffer circuit is provided,
The buffer circuit
An input terminal is connected to a control terminal of the first transistor and a control terminal of the second transistor, and an output terminal is connected to the first switch circuit and the second switch circuit. A differential amplifier circuit. The differential amplifier circuit according to any one of claims 1 to 6,
Furthermore, a buffer circuit is provided,
The buffer circuit
An input terminal is connected to the first switch circuit and the second switch circuit, and an output terminal is connected to a control terminal of the first transistor and a control terminal of the second transistor. A differential amplifier circuit. The differential amplifier circuit according to any one of claims 1 to 8,
A differential amplifier circuit, wherein a common connection point between the source terminal of the first transistor and the source terminal of the second transistor and the first power supply terminal are directly connected. The differential amplifier circuit according to any one of claims 1 to 8,
A differential amplifier circuit comprising a constant current source between a common connection point of the source terminal of the first transistor and the source terminal of the second transistor and the first power supply terminal.   11. A ring oscillator circuit comprising a plurality of differential amplifier circuits according to claim 1, wherein the oscillation frequency is controlled by setting an amount of current flowing through each differential amplifier circuit. .

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