JP3583359B2 - Logic level conversion circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a logic level conversion circuit for converting a logic level signal of an emitter-coupled logic circuit (ECL) into a logic level signal compatible with a CMOS logic circuit at high speed and accurately using a single power supply.
[0002]
[Prior art]
As a conventional logic level conversion circuit, for example, a circuit described in JP-A-6-196959 is known. FIG. 3 is an ECL / CMOS logic level conversion circuit diagram described in the above publication. Hereinafter, the conventional logic level conversion circuit will be described with reference to FIG.
[0003]
3 includes a current switch circuit 1, an emitter follower circuit 2, a common-gate PMOS amplifier circuit 5, and an output buffer circuit 6. The input terminal IN of the current switch circuit 1 has an ECL level input logic signal. Is applied, and a logic signal at the CMOS level is output from the output terminal OUT of the output buffer circuit 6. This logic signal output drives a CMOS gate, typically shown as CMOS load gate circuit 4. The CMOS load gate circuit 4 is a gate circuit such as a flip-flop driven by a logic level conversion circuit.
[0004]
The ECL level signal is input into the current switch 1 via a level shift by an emitter follower including the NPN transistor Q1 and the constant current source I1 in the current switch circuit 1. The current switch circuit 1 includes a pair of NPN transistors Q2 and Q3 forming a differential pair, resistors R1 and R2, and a constant current source I2 for controlling a common emitter current. A reference voltage Vbb that determines an input threshold is input to the base of the NPN transistor Q3.
[0005]
The emitter follower circuit 2 includes NPN transistors Q4 and Q5, receives the output of the current switch circuit 1 at its base, and outputs the output from each emitter to the common-gate PMOS amplifier circuit 5.
[0006]
The common-gate PMOS amplifier circuit 5 is configured by a base current extraction circuit including PMOS transistors MP1 and MP2 whose sources are driven and controlled, resistors R3 and R4, diodes D1 and D2, and an NMOS transistor MN1. A bias voltage Vgg is applied to the gates of the PMOS transistors MP1 and MP2.
[0007]
The output buffer circuit 6 includes NPN transistors Q9 and Q10 whose bases are connected to the drains of the PMOS transistors MP1 and MP2, and NMOS transistors MN2 and MN3 whose drains are connected to the emitters of the NPN transistors Q9 and Q10, respectively. It is configured. The NMOS transistors MN2 and MN3 operate as a current mirror circuit because their sources and gates are connected to each other.
[0008]
The CMOS load gate circuit 4 constitutes a CMOS inverter including a PMOS transistor MP and an NMOS transistor MN, and represents a large number of loads. Here, the high potential power supply Vdd (CMOS power supply) of the CMOS load gate circuit 4 is 2 Vf (Vf is a diode forward voltage) from the bipolar power supply Vcc in order to effectively use the signal amplitude from the output terminal OUT. A lowered potential is given.
[0009]
Next, an outline of the operation of the logic level conversion circuit of FIG. 3 will be described. The input signal having the ECL amplitude is input to the input terminal IN, and is output by the current switch circuit 1 as a complementary signal having an amplitude of about 1 [V]. This complementary signal is level-shifted by NPN transistors Q4 and Q5 in the emitter follower circuit 2, and sent to the next-stage source-driven PMOS transistors MP1 and MP2. The output impedance is reduced by passing through the emitter follower circuit 2, and the delay of the transmission time due to the input capacitance of the gates of the PMOS transistors MP1 and MP2 is reduced.
[0010]
A bias voltage Vgg is applied to each gate of the PMOS transistors MP1 and MP2, and a potential difference between the output of the emitter follower circuit 2 and the bias voltage Vgg is converted to a current output. The current flowing through the PMOS transistor MP1 is converted into a voltage by the resistor R3, the diode D1, and the NMOS transistor MN1, and is input to the base of the NPN transistor Q9. Similarly, the current flowing through the PMOS transistor MP2 is converted into a voltage by the resistor R4 and the diode D2, and is input to the base of the NPN transistor Q10.
[0011]
The resistor R3, the diode D1, and the NMOS transistor MN1 extract a base charge when the NPN transistor Q9 is turned off to increase an off speed, and a switch that is used when the base potential of the NPN transistor Q9 is too low in an off state. It has a function of suppressing a response delay at the time of ON. The resistor R4 and the diode D2 also have a function of extracting the base charge when the NPN transistor Q10 is off and increasing the off speed, and a function at the time of switch-on due to the base potential of the NPN transistor Q10 being too low in the off state. It has a function of suppressing a response delay.
[0012]
The emitters of the NPN transistors Q9 and Q10 are connected to a current mirror circuit composed of the NMOS transistors MN2 and MN3, so that the emitter amplitude and drive capability of the NPN transistor Q10 can be sufficiently ensured. In this way, an amplitude sufficient to sufficiently turn on / off the CMOS in the CMOS load gate circuit 4 is obtained.
[0013]
[Problems to be solved by the invention]
However, the above conventional technology has the following problems. That is, according to the conventional logic level conversion circuit, (1) the rise time of the base voltage of the NPN transistor Q9 is determined by the on-resistance of the PMOS transistor MP1 and the parasitic capacitance of the drain node of the PMOS transistor MP1. Therefore, the propagation delay time between the input and the output also becomes slow, and the demand for the delay time of the IC accompanying the recent increase in the data processing speed cannot be satisfied. (2) The logic signal from the output terminal OUT Since the output high level is low, a CMOS power supply Vdd and a bipolar power supply Vcc are required to drive the CMOS load gate. In order to set the CMOS power supply Vdd to 3 [V], the bipolar power supply Vcc needs to be (3 + 2 · Vf) [V] or more, which leads to an increase in power consumption. For example, when the bipolar power supply Vcc is set at 4.5 [V] and the CMOS power supply Vdd is set at 3 [V], the input terminal IN changes from high level to low level, and the output terminal changes from high level to low level. As a result of performing a simulation by SPICE, the delay time between input and output became longer than 1 [ns].
[0014]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a logic level capable of using a single power supply and converting a ECL level signal to a logic level compatible with a CMOS logic circuit at high speed and accurately. A conversion circuit is provided.
[0015]
[Means for Solving the Problems]
In order to solve the above problem, a logic level conversion circuit according to the present invention generates a complementary signal based on an ECL level signal, shifts the level of each of the complementary signals, and converts the ECL level signal into a CMOS logic level signal. The following measures are taken in the logic level conversion circuit.
[0016]
That is, the logic level conversion circuit includes: (a) a predetermined bias voltage is applied to the gate, and the first and the second signals driven by the signals having the opposite phase and the same phase as the ECL level signal among the level-shifted complementary signals, A second MOS transistor, and (b) first and second bipolar transistors connected between the first and second MOS transistors and ground, respectively, based on a current flowing through the first MOS transistor. And a current mirror circuit in which a base of each of the second bipolar transistors is driven.
[0017]
According to the above configuration, a complementary signal is generated based on the ECL level signal, and this complementary signal is level-shifted. The first MOS transistor is driven based on the difference between the level-shifted complementary signal having a reverse phase relationship with the ECL level signal and a predetermined bias voltage, and the first MOS transistor having the same phase relationship with the predetermined bias voltage. The second MOS transistor is driven based on the difference.
[0018]
These first and second MOS transistors are respectively connected to first and second bipolar transistors in a current mirror circuit, and bases of the first and second bipolar transistors are respectively set based on a current flowing through the first MOS transistor. Driven. As a result, the same current flows through each of the first and second bipolar transistors, and the output impedance of the second bipolar transistor changes according to the magnitude of the base current.
[0019]
For example, when the ECL level signal is at a low level, a high-level signal having a phase opposite to that of the ECL level signal among the level-shifted complementary signals is applied to the first MOS transistor. Accordingly, the current flowing through the first MOS transistor increases, and the current flowing through the first and second bipolar transistors increases. Thereby, the output impedance of the second bipolar transistor decreases.
[0020]
At this time, a low-level signal having the same phase as the ECL level signal among the level-shifted complementary signals is applied to the second MOS transistor. As a result, the current flowing through the second MOS transistor decreases, and the output impedance of the second MOS transistor increases.
[0021]
On the other hand, when the ECL level signal is at the high level, a low-level signal having a phase opposite to that of the ECL level signal among the level-shifted complementary signals is applied to the first MOS transistor. Accordingly, the current flowing through the first MOS transistor decreases, and the current flowing through the first and second bipolar transistors decreases. Thereby, the output impedance of the second bipolar transistor increases.
[0022]
At this time, a high-level signal in phase with the ECL level signal among the level-shifted complementary signals is applied to the second MOS transistor. Thus, the output impedance of the second MOS transistor decreases.
[0023]
As described above, when the ECL level signal is at a low level, the output impedance of the second MOS transistor increases and the output impedance of the second bipolar transistor decreases.
[0024]
When the ECL level signal is at a high level, the output impedance of the second MOS transistor decreases and the output impedance of the second bipolar transistor increases. That is, when the ECL level signal is at the high level, the output impedance of the second bipolar transistor increases. Therefore, if the connection point between the second bipolar transistor and the second MOS transistor is extracted as an output, the high level (CMOS logic level) High level) can be realized.
[0025]
Therefore, in the logic level conversion circuit, an output level sufficient to directly drive a CMOS load can be ensured, so that only a single type of CMOS power supply may be provided as an operation power supply. This can be avoided reliably (the conventional logic level conversion circuit can output only a low high-level output signal, and therefore requires two types of power supplies, which increases power consumption).
[0026]
Specifically, the logic level conversion circuit includes: (1) a current switch circuit that includes a pair of NPN transistors forming a differential pair and generates a complementary signal based on an ECL level signal; And (3) a predetermined bias voltage is applied to the gate to reverse the ECL level signal among the level-shifted complementary signals. A first and a second MOS transistor respectively driven by a phase and an in-phase signal; and a first and a second bipolar transistor respectively connected between the first and the second MOS transistor and the ground. Based on the current flowing through the first and second bipolar transistors. It is preferable that the scan is provided with an amplifier circuit having a current mirror circuit driven respectively.
[0027]
In this case, as described above, in the logic level conversion circuit, an output level sufficient to directly drive the CMOS load can be secured, so that only a single type of CMOS power supply need be provided as the operation power supply. Therefore, an increase in power consumption can be reliably avoided.
[0028]
The first MOS transistor preferably has a capacitor connected between the source and the drain. Among the level-shifted complementary signals, a signal having a phase opposite to that of the ECL level signal is applied to the first bipolar transistor via the first MOS transistor, and the on-resistance of the first MOS transistor and the node of the drain of the first MOS transistor are applied. Delay due to the time determined by the parasitic capacitance, which is not preferable from the viewpoint of increasing the data processing speed in recent years. Therefore, as described above, when a capacitor is connected between the source and the drain of the first MOS transistor, the change in the signal is propagated at a high speed through the capacitor, so that the delay time can be reliably reduced.
[0029]
It is preferable to provide a clamp circuit that clamps at a predetermined voltage so that the second bipolar transistor does not operate in a saturation region. When the output impedance of the second bipolar transistor is reduced and the voltage between both ends (voltage between the emitter and the collector) is reduced (when the second bipolar transistor operates in a saturation region), it takes time to recover from it, and the high-speed It is not preferable from the viewpoint of chemical conversion. Therefore, by providing the clamp circuit as described above, the second bipolar transistor is clamped at a predetermined voltage, so that the voltage at both ends can be reliably prevented from becoming unnecessarily small, and high-speed operation can be performed.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS. Members having the same functions as those of the logic level conversion circuit shown in FIG. 3 are denoted by the same reference numerals.
[0031]
As shown in FIG. 1, the logic level conversion circuit according to the present embodiment includes a current switch circuit 1, an emitter follower circuit 2, and a common-gate PMOS amplifier circuit 3, and an ECL is connected to an input terminal IN of the current switch circuit 1. A level input logic signal (ECL level signal) is applied, and a CMOS level logic signal is output from the output terminal OUT of the common-gate PMOS amplifier circuit 3. This logic signal output drives a CMOS gate, typically shown as CMOS load gate circuit 4. The CMOS load gate circuit 4 is a gate circuit such as a flip-flop driven by a logic level conversion circuit. The above-mentioned gate-grounded PMOS amplifier circuit 3 also has the function of the output buffer circuit 6 of the conventional logic level conversion circuit shown in FIG.
[0032]
The ECL level signal is input into the current switch 1 via a level shift by an emitter follower including the NPN transistor Q1 and the constant current source I1 in the current switch circuit 1. The current switch circuit 1 includes a pair of NPN transistors Q2 and Q3 forming a differential pair, resistors R1 and R2, and a constant current source I2 for controlling a common emitter current, and generates a complementary signal having an amplitude of about 1 [V]. I do. A reference voltage Vbb that determines an input threshold is input to the base of the NPN transistor Q3.
[0033]
The emitter follower circuit 2 includes NPN transistors Q4 and Q5, receives the output of the current switch circuit 1 at its base, and outputs the output from each emitter to the common-gate PMOS amplifier circuit 5.
[0034]
That is, of the complementary signals that have been level-shifted by the emitter follower circuit 2, the signals having the opposite phase and the same phase as the ECL level signal drive the sources of the PMOS transistors MP1 and MP2 (first and second MOS transistors), respectively. It is connected.
[0035]
The common-gate PMOS amplifier circuit 3 includes the source-controlled PMOS transistors MP1 and MP2, the NPN transistors Q6 and Q7 (first and second bipolar transistors) forming a current mirror circuit, and the source-drain of the PMOS transistor MP1. It comprises a capacitor C1 provided therebetween and an NPN transistor Q8 (clamp circuit) for preventing saturation of the NPN transistor Q7.
[0036]
The clamp voltage Vclp is applied to the base of the saturation preventing NPN transistor Q8. A bias voltage Vgg is applied to the gates of the PMOS transistors MP1 and MP2.
[0037]
The CMOS load gate circuit 4 constitutes a CMOS inverter including a PMOS transistor MP and an NMOS transistor MN, and represents a large number of loads. Here, a power supply Vcc (which is both a bipolar power supply and a CMOS power supply) is directly applied as a high-potential power supply of the CMOS load gate circuit 4.
[0038]
Here, the operation of the logic level conversion circuit will be described. The input signal at the ECL level is input to the input terminal IN, and a complementary signal having an amplitude of about 1 [V] is generated and output by the current switch circuit 1. This complementary signal is level-shifted by NPN transistors Q4 and Q5 in the emitter follower circuit 2, and sent to the next-stage source-controlled PMOS transistors MP1 and MP2. Output impedance is reduced by passing through the emitter follower circuit 2, thereby preventing a delay in transmission time due to the input capacitance of the gates of the PMOS transistors MP1 and MP2.
[0039]
In the common-gate PMOS amplifier circuit 3, the bias voltage Vgg is applied to each gate of the PMOS transistors MP1 and MP2, and a current mirror circuit including NPN transistors Q6 and Q7 is connected to each drain. As a result, a drain current corresponding to the voltage difference between the output of the emitter follower circuit 2 (the source voltage of the PMOS transistors MP1 and MP2) and the bias voltage Vgg flows through the PMOS transistors MP1 and MP2.
[0040]
The drain current of the PMOS transistor MP1 becomes the collector current of the NPN transistor Q6 and the respective base currents of the NPN transistors Q6 and Q7, and the output impedance of the NPN transistor Q7 changes with the change of the drain current.
[0041]
That is, for example, when a low level ECL level signal is applied to the input terminal IN, the source voltage of the PMOS transistor MP1 becomes high level. As described above, when the source voltage of the PMOS transistor MP1 becomes a high level, the voltage difference from the bias voltage Vgg increases, so that the drain current of the PMOS transistor MP1 increases. Accordingly, the base currents of NPN transistors Q6 and Q7 increase, and the collector currents of NPN transistors Q6 and Q7 also increase, so that the output impedance of NPN transistor Q7 decreases. If the load connected to the collector of the NPN transistor Q7 is the same, the voltage Vce between the collector and the emitter decreases.
[0042]
At this time, since the source voltage of the PMOS transistor MP2 is at the low level, the voltage between the source and the gate of the PMOS transistor MP2 is reduced, and the drain current of the PMOS transistor MP2 is reduced. As a result, the output impedance of the PMOS transistor MP2 increases.
[0043]
As described above, when the source voltage of the PMOS transistor MP1 goes high, the output impedance of the NPN transistor Q7 decreases and the output impedance of the PMOS transistor MP2 increases. (Low level) logic signal is output. When the low level logic signal is received, the CMOS load gate circuit 4 outputs a high level signal by turning on the PMOS transistor MP and turning off the NMOS transistor MN.
[0044]
On the other hand, when a high level ECL level signal is applied to the input terminal IN, the source voltage of the PMOS transistor MP1 becomes low level. As described above, when the source voltage of the PMOS transistor MP1 becomes low level, the voltage difference from the bias voltage Vgg becomes smaller, so that the drain current of the PMOS transistor MP1 becomes smaller. Accordingly, the base current of NPN transistors Q6 and Q7 decreases, and the collector current of NPN transistors Q6 and Q7 also decreases, so that the output impedance of NPN transistor Q7 increases. If the load connected to the collector of the NPN transistor Q7 is the same, the voltage Vce between the collector and the emitter increases.
[0045]
At this time, since the source voltage of the PMOS transistor MP2 is at the high level, the source-gate voltage of the PMOS transistor MP2 increases, and the drain current of the PMOS transistor MP2 increases. As a result, the output impedance of the PMOS transistor MP2 decreases.
[0046]
As described above, when the source voltage of the PMOS transistor MP1 goes low, the output impedance of the NPN transistor Q7 increases and the output impedance of the PMOS transistor MP2 decreases. (High level) logic signal is output. When receiving the high-level logic signal, the CMOS load gate circuit 4 turns off the PMOS transistor MP and turns on the NMOS transistor MN to output a low-level signal.
[0047]
In the above description, if the collector potential of the NPN transistor Q7 is too low (the voltage Vce between the collector and the emitter is too low) and enters the saturation region (operates in the saturation region), It will take time to recover from the condition. Therefore, in the present invention, a clamp circuit including an NPN transistor Q8 is provided in order to prevent the collector potential of the NPN transistor Q7 from being too low.
[0048]
The clamp circuit has a configuration in which the emitter of the NPN transistor Q8 is connected to the collector of the NPN transistor Q7, the clamp voltage Vclp is applied to the base of the NPN transistor Q8, and the power supply Vcc is applied to the collector of the NPN transistor Q8. . Thus, when a low level (low level of CMOS logic level) is output from the output terminal OUT, the collector potential of the NPN transistor Q7 is clamped to (Vclp-Vf) (Vf is the base-emitter of the NPN transistor Q8). Between the forward voltage drops.)
[0049]
For example, assuming that the clamp voltage Vclp is 2 Vf, when a high level (CMOS logic level high level) is output from the output terminal OUT, this high level voltage is (Vcc-Vf). On the other hand, when a low level (CMOS logic level low level) is output from the output terminal OUT, the low level voltage is (2Vf-Vf) = Vf. That is, at this time, since the amplitude can be increased from Vf to (Vcc-Vf), it is not necessary to separately provide two types of power supplies Vcc and Vdd (that is, only with a single power supply Vcc) as in the related art. An amplitude sufficient to drive the PMOS transistor MP and the NMOS transistor MN of the CMOS load gate circuit 4 can be secured. Therefore, according to the logic level conversion circuit, an output level sufficient to directly drive a CMOS load can be ensured, so that only a single type of CMOS power supply needs to be provided as an operation power supply. Therefore, it is not necessary to provide two power supplies separately, and an increase in power consumption can be reliably avoided.
[0050]
In the present invention, the capacitor C1 is provided between the source and the drain of the PMOS transistor MP1, which will be described here.
[0051]
The capacitor C1 is provided to quickly raise the drain voltage to a high level when the source voltage of the PMOS transistor MP1 is at a high level. The capacitor C1 functions as a high-pass filter. In this case, as is apparent from FIG. 2, it is possible to suppress the input / output propagation delay time that occurs when transitioning from a high level to a low level (both are CMOS logic levels) to 1 [ns] or less.
[0052]
As described above, according to the logic level conversion circuit of the present invention, when performing ECL / CMOS logic level conversion, the ECL / CMOS power supply is kept common (ie, a single power supply is used), An ECL level signal that transitions from level to low level can be quickly converted to a logic level suitable for a CMOS logic circuit. For example, when transitioning from the high level to the low level at the ECL level at the input terminal IN, Vcc = 3 [V], Vgg = 0.5 [V], Vclp = 1.4 [V], C1 = 3 pF (capacitor C1 The capacitance was C1.), And the simulation by SPICE was performed. As a result, the input / output propagation delay time was 1 [ns].
[0053]
It is needless to say that the present invention is not limited to the configuration shown in FIG. 1, but may be any configuration that can realize the same operation.
[0054]
【The invention's effect】
As described above, the logic level conversion circuit according to the present invention includes: (a) a predetermined bias voltage is applied to the gate, and the ECL level signal is in phase and in phase with the ECL level signal among the level-shifted complementary signals. (B) first and second bipolar transistors connected between the first and second MOS transistors and the ground, respectively; and (b) a current flowing through the first MOS transistor. And a current mirror circuit in which the bases of the first and second bipolar transistors are respectively driven.
[0055]
According to the above configuration, the first and second MOS transistors are respectively connected to the first and second bipolar transistors in the current mirror circuit, and the first and second bipolar transistors are based on the current flowing through the first MOS transistor. Are respectively driven. As a result, the same current flows through each of the first and second bipolar transistors, and the output impedance of the second bipolar transistor changes according to the magnitude of the base current.
[0056]
For example, when the ECL level signal is at a low level, a high-level signal having a phase opposite to that of the ECL level signal among the level-shifted complementary signals is applied to the first MOS transistor. Accordingly, the output impedance of the second bipolar transistor decreases. At this time, a low-level signal having the same phase as the ECL level signal among the level-shifted complementary signals is applied to the second MOS transistor. As a result, the output impedance of the second MOS transistor increases.
[0057]
On the other hand, when the ECL level signal is at the high level, a low-level signal having a phase opposite to that of the ECL level signal among the level-shifted complementary signals is applied to the first MOS transistor. Accordingly, the output impedance of the second bipolar transistor increases. At this time, a high-level signal in phase with the ECL level signal among the level-shifted complementary signals is applied to the second MOS transistor. Thus, the output impedance of the second MOS transistor decreases.
[0058]
As described above, when the ECL level signal is at a low level, the output impedance of the second MOS transistor increases and the output impedance of the second bipolar transistor decreases.
[0059]
When the ECL level signal is at a high level, the output impedance of the second MOS transistor decreases and the output impedance of the second bipolar transistor increases. That is, when the ECL level signal is at the high level, the output impedance of the second bipolar transistor increases. Therefore, if the connection point between the second bipolar transistor and the second MOS transistor is drawn as an output, the high level (CMOS logic level) High level) can be realized.
[0060]
Therefore, in the logic level conversion circuit, an output level sufficient to directly drive a CMOS load can be ensured, so that only a single type of CMOS power supply may be provided as an operation power supply. This has the effect that it can be avoided reliably.
[0061]
Specifically, the logic level conversion circuit includes: (1) a current switch circuit that includes a pair of NPN transistors forming a differential pair and generates a complementary signal based on an ECL level signal; And (3) a predetermined bias voltage is applied to the gate to reverse the ECL level signal among the level-shifted complementary signals. A first and a second MOS transistor respectively driven by a phase and an in-phase signal; and a first and a second bipolar transistor respectively connected between the first and the second MOS transistor and the ground. Based on the current flowing through the first and second bipolar transistors. It is preferable that the scan is provided with an amplifier circuit having a current mirror circuit driven respectively.
[0062]
In this case, in the logic level conversion circuit, an output level sufficient to directly drive the CMOS load can be secured, so that a single type of CMOS power supply may be provided as an operation power supply, and therefore, power consumption increases. Can be reliably avoided.
[0063]
The first MOS transistor preferably has a capacitor connected between the source and the drain. Among the level-shifted complementary signals, a signal having a phase opposite to that of the ECL level signal is applied to the first bipolar transistor via the first MOS transistor, and the on-resistance of the first MOS transistor and the node of the drain of the first MOS transistor are applied. Delay due to the time determined by the parasitic capacitance, which is not preferable from the viewpoint of increasing the data processing speed in recent years. Therefore, as described above, if a capacitor is connected between the source and the drain of the first MOS transistor, the change in the signal is propagated at a high speed through the capacitor, so that the delay time can be reliably reduced. Play.
[0064]
It is preferable to provide a clamp circuit that clamps at a predetermined voltage so that the second bipolar transistor does not operate in a saturation region. When the output impedance of the second bipolar transistor is reduced and the voltage between both ends (voltage between the emitter and the collector) is reduced (when the second bipolar transistor operates in a saturation region), it takes time to recover from it, and the high-speed It is not preferable from the viewpoint of chemical conversion. Therefore, as described above, by providing the clamp circuit, the second bipolar transistor is clamped at a predetermined voltage, so that the voltage at both ends can be reliably prevented from becoming unnecessarily small, and high-speed operation can be performed. It also has an effect.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of a logic level conversion circuit according to the present invention.
FIG. 2 is a graph showing a simulation result by SPICE showing an input / output propagation delay time of the logic level conversion circuit.
FIG. 3 is a circuit diagram showing a configuration example of a conventional logic level conversion circuit.
FIG. 4 is a graph showing a simulation result by SPICE showing an input / output propagation delay time of a conventional logic level conversion circuit.
[Explanation of symbols]
1 Current switch circuit
2 Emitter follower circuit
3 Common gate PMOS amplifier circuit
MP1 PMOS transistor (first MOS transistor)
MP2 PMOS transistor (second MOS transistor)
Q6 NPN transistor (first bipolar transistor)
Q7 NPN transistor (second bipolar transistor)
Q8 NPN transistor for preventing saturation (clamp circuit)
C1 capacitor

Claims (4)

A logic level conversion circuit that generates a complementary signal based on the ECL level signal, shifts the level of the complementary signal, and converts the ECL level signal into a CMOS logic level signal.
A first and second MOS transistors driven by a signal having a predetermined bias voltage applied to the gate thereof and having the opposite phase and the same phase as the ECL level signal among the level-shifted complementary signals;
The first and second bipolar transistors are connected between the first and second MOS transistors and the ground, respectively, and the bases of the first and second bipolar transistors are respectively set based on the current flowing through the first MOS transistor. And a driven current mirror circuit. A current switch circuit comprising a pair of NPN transistors forming a differential pair and generating a complementary signal based on the ECL level signal;
An emitter follower circuit comprising an NPN transistor provided for each of the complementary signals, for level-shifting the complementary signals,
A first and second MOS transistor driven by a signal having a phase opposite to and the same as the ECL level signal among the level-shifted complementary signals having a predetermined bias voltage applied to the gate; and the first and second MOS transistors, respectively. A current mirror circuit comprising first and second bipolar transistors respectively connected between the first and second bipolar transistors, the bases of the first and second bipolar transistors being driven based on current flowing through the first MOS transistor, respectively. A logic level conversion circuit comprising: an amplification circuit having: 3. The logic level conversion circuit according to claim 1, wherein a capacitor is connected between the source and the drain of the first MOS transistor. 4. The logic level conversion circuit according to claim 3, further comprising a clamp circuit that clamps at a predetermined voltage so that the second bipolar transistor does not operate in a saturation region.

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