JP3060621B2 - Semiconductor level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor level conversion circuit, and more particularly to a semiconductor level conversion circuit for matching a logic level between an ECL circuit and a CMOS circuit of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a recent semiconductor circuit, more than one million transistors can be integrated on one chip by a technology for miniaturizing a MOS transistor. In addition, Bi-CMOS type integrated circuits, in which a bipolar element and a CMOS element are mixed on a single chip and have the characteristics of each other, have come to be frequently used.

In such a Bi-CMOS circuit, an ECL (Emitter Coupler) capable of operating at high speed is used.
A high-speed and low-power-consumption logic circuit can be realized by combining a low-logic (led Logic) circuit and a low-power-consumption CMOS circuit. However, since the ECL circuit and the CMOS circuit have different logic levels, when these circuits are connected, a circuit for converting the logic level must be provided therebetween.

FIG. 3 shows a semiconductor level conversion circuit using a pair of emitter follower circuits to which complementary input signals, which are often used as load driving buffers in an ECL circuit, are respectively applied.

FIG. 4 shows operation waveforms of this circuit. IN
When input signals (logic amplitude is ΔV1) of complementary ECL levels of IN1 and IN2 are applied to the bases of the bipolar transistors Q1 and Q2, the emitters serving as output terminals are connected to the emitters.
The output signal OU lower than the input signals IN1 and IN2 by the forward junction voltage Vbe (about 0.8 V) between the base and the emitter.
T1 and OUT2 can be taken out.

[0006]

However, in this semiconductor level conversion circuit, the output signals OUT1, OUT
The constant current circuits 2a and 2b are used for the fall of 2, and the current is constantly consumed irrespective of the state of the input signals IN1 and IN2. It was difficult. Also, output signals OUT1, OUT1
2 is equivalent to the amplitudes of the input signals IN1 and IN2. In an integrated circuit in which an ECL circuit and a CMOS circuit are mixed, the output of the ECL circuit is changed to a CMOS circuit (the signal amplitude is about the power supply amplitude). There is a case where an input is desired, but at this time, there is a disadvantage that an ECL-CMOS level conversion circuit is required between the circuit of FIG. 4 and the CMOS circuit.

An object of the present invention is to provide an ECL for an emitter follower.
-To provide a semiconductor level conversion circuit capable of realizing high integration and high speed of the circuit and realizing low power consumption by adding a CMOS level conversion function.

[0008]

A semiconductor level conversion circuit according to the present invention comprises a first bipolar transistor for inputting a first input signal to a base, and a second input complementary to the first input signal for a base. A second bipolar transistor for inputting a signal, a first MIS transistor of one conductivity type and a second MIS transistor of the opposite conductivity type, and an input terminal connected to the emitter of the second bipolar transistor, A first emitter follower circuit is formed together with the bipolar transistor, and an output terminal of the first current follower circuit is used as an output terminal of the first emitter follower circuit.
And a third MIS transistor of one conductivity type and a fourth MIS transistor of the opposite conductivity type, having an input terminal connected to the emitter of the first bipolar transistor and a second emitter follower together with the second bipolar transistor. And a complementary second inverter of a second current source circuit having a circuit formed and having an output terminal as an output terminal of the second emitter follower circuit.

[0009]

According to the present invention, the low level of the output signal can be reduced to the _VEE level by making the constant current source circuit connected to the emitter of the bipolar transistor a complementary inverter. High level is equivalent to the high level output of the emitter. Therefore, a signal amplitude that can be directly input to the CMOS circuit is obtained. In addition, since the current for lowering the emitter level flows only to the side of the bipolar transistor outputting a high level, the current consumption can be reduced by half.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the first input signal I
A first bipolar transistor Q1 for inputting N1;
A second bipolar transistor Q2 that inputs a second input signal IN2 complementary to the first input signal IN1 to the base
And a P-type first MIS transistor MP1 and an N-type second MIS transistor MN1 having an input terminal connected to the emitter of the second bipolar transistor Q2 to form a first emitter follower circuit together with the first bipolar transistor Q1. A complementary first inverter 1a of a first current source circuit formed and having an output terminal as an output terminal of the first emitter follower circuit, and a P-type third MIS transistor MP2
And an N-type fourth MIS transistor MN2, the input terminal of which is connected to the emitter of the first bipolar transistor Q1 to form a second emitter follower circuit together with the second bipolar transistor Q2, and the output terminal of which is connected to the second emitter follower circuit. And a complementary second inverter 1b of the second current source circuit as an output terminal of the second current source circuit.

Next, the operation of this embodiment will be described. FIG. 2 is a waveform chart of voltages and currents of signals of respective parts for explaining the operation of this embodiment.

In this embodiment, when the input signal IN1 is at a high level, the MIS transistor MN2 is turned on,
The S transistor MP2 is turned off, and the output signal OUT2
Is at the _VEE level as shown in FIG. At this time, the current I _CQ2 flowing through the bipolar transistor Q2 is “0”.
Becomes At the same time, since the input signal IN2 is at a low level, the MIS transistor MP1 is turned on, and the output signal OUT1 is at a level equivalent to the level of the emitter of the bipolar transistor Q1. At this time, the MIS transistor MN1 does not turn off completely when the input amplitude is smaller than the power supply amplitude, such as at the ECL level, and the current I _CQ1 flows through the bipolar transistor Q1.

However, this is the current required to quickly lower the emitter of bipolar transistor Q1 at a high speed. In the conventional example shown in FIG. 4, constant current sources 2a and 2
This is the current flowing through b. However, since this current flows only to the side of the bipolar transistor that outputs a high level, the current consumption can be reduced by half as compared with the conventional example.

[0016]

As described above, according to the present invention, a first current source circuit forming a first emitter follower circuit together with a first bipolar transistor is connected to an input terminal connected to the emitter of the second bipolar transistor. A second current source circuit comprising a first inverter of a first bipolar transistor and forming a second emitter follower circuit together with a second bipolar transistor; and a second complementary current source circuit having an input terminal connected to the emitter of the first bipolar transistor. In the conventional example, current flows through the current source circuit even at the time of low-level output, but in the present invention, current does not flow through the current source circuit at the time of low-level output, so that power consumption is reduced. And these emitter follower circuits are EC
Since it has an L-CMOS level conversion function, there is an effect that high integration and high speed of the circuit can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram of voltages and currents of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor level conversion circuit.

FIG. 4 is a voltage waveform diagram of signals of respective parts for describing an operation of the semiconductor level conversion circuit shown in FIG. 3;

[Explanation of symbols]

1a, 1b Inverter 2a, 2b Constant current source circuit MN1, MN2, MP1, MP2 MIS transistor Q1, Q2 Bipolar transistor

Claims (1)

(57) [Claims] A first input signal input to a base;
Bipolar transistor, a second bipolar transistor whose base receives a second input signal complementary to the first input signal, a first MIS transistor of one conductivity type and a second MIS transistor of opposite conductivity type A first current source having an input terminal connected to the emitter of the second bipolar transistor, forming a first emitter follower circuit together with the first bipolar transistor, and having an output terminal as an output terminal of the first emitter follower circuit. A first inverter of a complementary type of the circuit, a third MIS transistor of one conductivity type and a fourth MIS transistor of the opposite conductivity type, and an input terminal connected to the emitter of the first bipolar transistor; A second emitter follower circuit is formed together with the bipolar transistor, and the output terminal is connected to the output of the second emitter follower circuit. Semiconductor level converting circuit, wherein further comprising a second inverter of the complementary type of the second current source circuit to the end.