JP2947218B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to an ECL (Emit
ter Coupled Logic) level signal amplitude to CMOS (Co
The present invention relates to an ECL-CMOS level conversion circuit that converts a signal amplitude into a signal amplitude of a level of mplimentary metal oxide semiconductor (Metal Oxide Semiconductor).

[0002]

2. Description of the Related Art A semiconductor integrated circuit device is constituted by combining a CMOS circuit having advantages of low power consumption and high integration and an ECL circuit having advantages of high-speed operation, thereby providing a logic circuit having both advantages. Is used. However, in a circuit sharing the ECL circuit and the CMOS circuit, a level conversion circuit for converting an ECL level signal into a CMOS level signal is indispensable. Also,
Recently, devices such as pagers that operate on a single dry battery are rapidly spreading, and it is necessary to reduce the voltage of the level conversion circuit used in this type of device. Have been.

FIG. 11 is a diagram showing a configuration of an example of a conventional level conversion circuit. FIG. 12 is a diagram showing a waveform example at the inputs IN and INB of the level conversion circuit shown in FIG. FIG. 13 is a diagram illustrating a waveform example at the node E of the level conversion circuit illustrated in FIG. FIG.
FIG. 6 is a diagram showing a waveform example at a node F of the level conversion circuit shown in FIG. FIG. 15 is a diagram illustrating a waveform example at the node OUT of the level conversion circuit illustrated in FIG.

First, the structure of the level conversion circuit shown in FIG. 11 will be described. The level conversion circuit shown in FIG. 11 includes a differential transistor circuit 71, a logic amplitude amplification circuit 72,
The configuration includes a CMOS inverter 73.
The differential transistor circuit 71 has an ECL level input I
Transistors Q1, Q forming a differential pair receiving N, INB
2, a load resistance R1, R2, and a constant current source IDD1. The logic amplitude amplification circuit 72 has a collector and a base connected to the node E of the differential transistor circuit 71.
A transistor Q3 connected to the collector of the transistor Q2 and having the emitter grounded, a transistor Q4 having a base connected to the base of the transistor Q3 and having the emitter grounded, and a voltage source VD at one end.
And a resistor R3 connected to the collector of the transistor Q4 whose other end is connected to the node D. The CMOS inverter 73 receives the node F, which is the output of the logic amplitude amplifier circuit 72, as an input, and
Output at the CMOS level.

Next, the operation of the level conversion circuit shown in FIG. 11 will be described assuming that the power supply voltage is 1V. It is assumed that a signal as shown in FIG. 12 is input to IN and INB of the differential transistor circuit 71, for example. At this time, since the bipolar transistor requires a collector-emitter voltage of about 0.2 V per stage in setting the DC operating point, the low level of the node E, which is the output of the differential transistor circuit 71, is low. Due to the collector-emitter voltage of the transistor Q2 and the voltage drop of the current source IDD1, the voltage is limited to 0.2 V or more as shown in FIG. 13, and the voltage drop is reduced by the amount that the transistor Q3 is turned on and the current flows through the resistor R2. Then, the high level becomes about 0.7V.

However, when the transistors Q3 and Q4 are on, the voltage at the node F, which is the output of the logic amplitude amplifier circuit 72, prevents the setting of the DC operating point of the transistor Q4 by the resistor R3, as shown in FIG. The voltage can be reduced to a voltage (about 0.2 V) that is not so high. When the transistors Q3 and Q4 are off, the high level increases to 1.0V. For this reason, 1.0V / 0.2V (high / low) 0.8
Since a signal having a logic amplitude of V can be input to the CMOS inverter 73, the next-stage CMOS inverter 73 can be sufficiently turned on and off, and a CMOS level full swing output is applied to the node OUT as shown in FIG. Can be obtained.

FIG. 16 is a diagram showing the configuration of another example of a conventional level conversion circuit, showing an embodiment of the invention of the level conversion circuit described in Japanese Patent Application Laid-Open No. 2-86318.

First, the configuration of the level conversion circuit shown in FIG. 16 will be described. The level conversion circuit shown in FIG. 16 includes a differential transistor circuit 121, a first level shift circuit 122, a second level shift circuit 123, and a first C
MOS output circuit 124 and second CMOS output circuit 12
5 is provided. The differential transistor circuit 121 includes transistors Q1, Q2 forming a differential pair receiving inputs IN, INB at the ECL level, and load resistors R1,
R2 and a constant current source IDD1 are provided. The first level shift circuit 122 includes a transistor Q3 having a base connected to the collector (node G) of the transistor Q1 of the differential transistor circuit 121 and a collector connected to the voltage source VDD, and one end connected to the transistor Q1.
A resistor R3 having the other end connected to one end (node I) of the current source IDD2, and a current source IDD2 having one end connected to one end (node I) of the resistor R3 and the other end grounded. And a configuration including: The base of the second level shift circuit 123 is the collector (node H) of the transistor Q2 of the differential transistor circuit 121.
, A collector connected to the voltage source VDD, a resistor R4 having one end connected to the emitter of the transistor Q4 and the other end connected to one end (node J) of the current source IDD3, and one end connected to the resistor. Current source IDD connected to one end (node J) of R4 and the other end is grounded
3 is provided. The first CMOS output circuit 124 has a gate connected to the node G of the differential transistor circuit 121 and a source connected to the voltage source VDD, and a gate connected to the node I of the first level shift circuit 122. The drain is Pc
An Nch MOSFET MN1 connected to the drain of the hMOSFET MP1 and having a source grounded is provided. The drains of the MP1 and MN1 serve as a node OUT. The second CMOS output circuit 125 has a PchMOS whose gate is connected to the node H of the differential transistor circuit 121 and whose source is connected to the voltage source VDD.
The FET MP2 and the gate are connected to the second level shift circuit 12
3 is connected to the node J and the drain is a Pch MOSFET
N connected to the drain of MP2 and the source is grounded
chMOSFET MN2.
The drains of MP2 and MN2 become node OUTB.

Next, the operation of the level conversion circuit shown in FIG. 16 will be described. The output signal of the differential transistor circuit 121 is directly input to the gates of the Pch MOSFETs MP1 and MP2. The NchMOSFET MN1 has a first
Of the transistor Q3 in the level shift circuit 122 of FIG. NchMOSFETMN
2 is input with its level shifted by the voltage between the base and the emitter of the transistor Q4 of the second level shift circuit 123 and the voltage drop by the resistor R4.

Therefore, the first level shift circuit 12
Even when the input signal supplied to the base of the second transistor Q3 is at a low level, the gate of the Nch MOSFET MN1 is connected to the base of the transistor Q3 from that level.
Since a voltage lower by the voltage between the emitter and the voltage drop in the resistor R3 is supplied, a state substantially close to the off state can be achieved. Thereby, the Pch MOSFET MP which is turned on by the low level signal
Since the on-resistance ratio to 1 can be increased, a stable high-level signal can be obtained. This means that the transistor Q4 of the second level shift circuit 123
The same applies when a low-level signal is input to the base of. When the input signal is at a high level, Pch
Since the gate and the source of the MOSFET MP1 or MP2 have the same potential as the power supply voltage, they are completely turned off,
A stable low-level signal can be obtained. Therefore, a CMOS-level full swing signal of differential logic can be obtained at the node OUT and the node OUTB.

[0011]

In the conventional level conversion circuit shown in FIG. 11, since the loads on the transistors Q1 and Q2 of the differential transistor circuit 71 are not equal, the collectors of the transistors Q1 and Q2 when the DC operating point is set are set. Since the currents are different and the base-emitter voltages of the respective transistors are different, the input offset voltage of the differential transistor circuit 71 becomes large. Transistor circuit 71
The disadvantage is that you have to enter the In addition, since there is only one output, there is a drawback that a circuit for generating a differential signal must be added when the next CMOS circuit requires a differential signal.

On the other hand, in the conventional level conversion circuit shown in FIG. 16, under a low voltage condition of about 1 V used in a pager or the like, the first or second level shift circuit 122,
After setting the DC operating point of 123, the base-emitter voltage (about 0.7 V) of the transistor Q3 or Q4, the resistor R3 or R4, and the constant current source IDD2 or ID
In consideration of the voltage drop of D3, the voltage becomes approximately 1 V only by these voltages. Therefore, the output amplitude of the differential transistor circuit 121 can hardly be obtained, and the level conversion circuit does not operate.

An object of the present invention is to solve the above-mentioned drawbacks and to provide
An object of the present invention is to provide a level conversion circuit that operates at a low voltage of about V, reduces an input offset voltage, and can obtain an output of a differential logic.

[0014]

A level conversion circuit according to the present invention comprises a differential transistor circuit (11) for inputting an ECL level logical amplitude signal, and a differential transistor circuit (1).
1) a first logic amplitude amplifier circuit (12) that receives the first output signal (A) and amplifies the logic amplitude of the first output signal (A); A second logical amplitude amplifier (13) for receiving the second output signal (B) and amplifying the logical amplitude of the second output signal (B); and a second logical amplitude amplifier (12). A first CMOS inverter (14) that receives a third output signal (C) and outputs a CMOS level signal (OUT); and a fourth output signal (2) of the second logic amplitude amplifier (13). D), and a second CMOS inverter (15) for outputting a CMOS level signal (OUTB).
The output signal (OUT) of the MOS inverter (14) and the output signal (OUT) of the second CMOS inverter (15)
B) is a differential logic.

In the level conversion circuit according to the present invention, the differential transistor circuit (11) includes a first transistor (Q1) and a second transistor (Q1) forming a differential pair for receiving an ECL level input signal (IN, INB). A transistor (Q2), a first resistor (R1) and a second resistor (R
2) and a current source (IDD1) having one end grounded. The first transistor (Q1) has a collector connected to one end of the first resistor (R1), and a base connected to the first resistor (R1). , The emitter is connected to the other end of the current source (IDD1), the first resistor (R1) is connected to one end of the first transistor (Q1).
And the other end is connected to a voltage source (VDD). The collector potential of the first transistor (Q1) is the first output signal (A), and the second transistor (Q2 ) Has a collector connected to one end of the second resistor (R2), a base connected to a second ECL level input signal (IN), and an emitter connected to the current source (IDD).
1), the second resistor (R2) is connected at one end to the collector of the second transistor (Q2), and the other end is connected to the voltage source (VDD); The collector potential of the second transistor (Q2) is the second output signal (B), and the first logical amplitude amplifying circuit (1
2) has a third transistor (Q3), a fourth transistor (Q4), and a third resistor (R3), and the third transistor (Q3) has a collector and a base connected to the first transistor (R3).
Of the transistor (Q1), the emitter thereof is grounded, the fourth transistor (Q4) has a collector connected to one end of the third resistor (R3), and has a base connected to the third transistor (R3). Connected to the base of Q3),
An emitter is grounded, the third resistor (R3) is connected at one end to the collector of the fourth transistor (Q4),
The other end is connected to the voltage source (VDD), and the collector potential of the fourth transistor (Q4) is the third output signal (C), and the second logical amplitude amplifier (13)
Has a fifth transistor (Q5), a sixth transistor (Q6), and a fourth resistor (R4), and the fifth transistor (Q5) has a collector and a base connected to the second transistor (R5). (Q2), the emitter is grounded, the sixth transistor (Q6) has a collector connected to one end of the fourth resistor (R4), and the base is the fifth transistor (Q5). The fourth resistor (R4) is connected at one end to the collector of the sixth transistor (Q6), and the other end is connected to the voltage source (VDD), The collector potential of the sixth transistor (Q6) is the fourth output signal (D).

In the level conversion circuit according to the present invention, the first logic amplitude amplifier (62) may include a fifth resistor (R).
5), the second logic amplitude amplifier (63) has a sixth resistor (R6), and the third transistor (Q
3) the collector is connected to one end of the fifth resistor (R5), the base is connected to the collector of the first transistor (Q1), the emitter is grounded, and the fifth resistor (R5) The other end is connected to the collector of the first transistor (Q1), and the fifth transistor (Q5)
Has a collector connected to one end of the sixth resistor (R6), a base connected to the collector of the second transistor (Q2), an emitter grounded, and a resistor connected to the sixth resistor (R6).
The other end of 6) can be connected to the collector of the second transistor (Q2).

Further, the above-mentioned level conversion circuit of the present invention
One end of the third resistor (R3) having a seventh resistor (R7) and one end connected to the collector of the fourth transistor (Q4) is connected to one end of the seventh resistor (R7). And the other end of the fourth resistor (R4), one end of which is connected to the collector of the sixth transistor (Q6), is connected to one end of the seventh resistor (R7). The other end of the resistor (R7) can be connected to the voltage source (VDD).

With the above-described configuration, it is possible to operate at a low voltage of about 1 V, reduce the input offset voltage of an ECL level input signal, and obtain a differential logic CMOS level signal output. . In addition, a feedback effect is obtained, and even when the power supply voltage fluctuates, a fluctuation in the value of the current flowing through the transistor Q4 or Q6, which is a current source, is suppressed to be small, and a stable operation can be realized.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing a waveform example at the inputs IN and INB of the level conversion circuit shown in FIG. FIG. 3 is a diagram showing a waveform example at nodes A and B of the level conversion circuit shown in FIG.
FIG. 4 is a diagram showing a waveform example at nodes C and D of the level conversion circuit shown in FIG. FIG. 5 is a diagram showing an example of waveforms at nodes OUT and OUTB of the level conversion circuit shown in FIG.

First, the configuration of the level conversion circuit shown in FIG. 1 will be described. The level conversion circuit shown in FIG. 1 includes a differential transistor circuit 11 and a first logical amplitude amplifier circuit 12.
, A second logical amplitude amplifier circuit 13, a first CMOS inverter 14, and a second CMOS inverter 15. The differential transistor circuit 11
The configuration includes transistors Q1 and Q2 forming a differential pair receiving inputs IN and INB at the ECL level, load resistors R1 and R2, and a constant current source IDD1. The first logic amplitude amplifying circuit 12 has a collector and a base connected to the collector (node A) of the transistor Q1 of the differential transistor circuit 11 and an emitter grounded, and a base connected to the base of the transistor Q3. The transistor Q4 has an emitter connected to the ground, and a resistor R3 having one end connected to the voltage source VDD and the other end connected to the collector (node C) of the transistor Q4. The second logical amplitude amplifier 13 includes a transistor Q5 whose collector and base are connected to the collector (node B) of the transistor Q2 of the differential transistor circuit 11, and whose emitter is grounded;
A transistor Q6 serving as a current source having a base connected to the base of the transistor Q5 and an emitter grounded; a resistor R4 having one end connected to the voltage source VDD and the other end connected to the collector (node D) of the transistor Q6; Is provided. First CMOS inverter 14
Is the node C which is the output of the first logical amplitude amplifier circuit 12.
Is output to the node OUT at the CMOS level. The second CMOS inverter 15 receives the node D, which is the output of the second logic amplitude amplifier circuit 13, as an input, and outputs a CMOS level to the node OUTB.

Next, the operation of the level conversion circuit shown in FIG. 1 will be described, particularly when the power supply is a 1 V power supply. It is assumed that the signals shown in FIG. 2 are input to IN and INB of the differential transistor circuit 11, for example. At this time, the low level of the nodes A and B, which are the outputs of the differential transistor circuit 11, is limited to 0.2 V or more as shown in FIG. The high level is about 0.7 V because the transistor Q3 or Q5 is turned on and a current drops through the resistor R1 or R2 to allow a current to flow.

However, the voltage at the node C, which is the output of the first logical amplitude amplifier 12, and the voltage at the node D, which is the output of the second logical amplitude amplifier 13, are as shown in FIG.
When the transistors Q3 and Q4 or Q5 and Q6 are on, the voltage may be reduced to a voltage (about 0.2 V) that does not prevent the setting of the DC operating point of the transistor Q4 or Q6 by the resistor R3 or R4. it can. When transistors Q3 and Q4 or Q5 and Q6 are off, the voltage rises to 1.0V. Therefore, the first CMOS inverter 14 and the second CMOS inverter 15 have a voltage of 1.0 V /
Since a signal having a logic amplitude of 0.8 V, which is 0.2 V (high / low), can be inputted, the next-stage CMOS inverter can be sufficiently turned on / off, and as shown in FIG. A CMOS output full swing output of differential logic can be obtained at OUT and the node OUTB.

Since the loads on the transistors Q1 and Q2 of the differential transistor circuit 11 are equal, the collector currents of the transistors Q1 and Q2 when the DC operating point is set are equal, and the base-emitter voltages of the respective transistors are equal. Therefore, the input offset voltage of the differential transistor circuit 11 can be reduced.

As described above, the circuit of the present invention can convert the input signal of the ECL level into a CMOS level signal of the differential logic while reducing the input offset voltage of the input signal even under a low voltage condition of about 1 V. it can.

FIG. 6 is a diagram showing a configuration of a level conversion circuit according to the second embodiment of the present invention.
Is a circuit corresponding to the level conversion circuit in the first embodiment shown in FIG. In the configuration of FIG. 6, description of the same parts as in the configuration of FIG. 1 is omitted. In FIG. 6, FIG.
The difference from the first embodiment is that the collector of the transistor Q3 of the first logic amplitude amplifier circuit 62 is not directly connected to the collector of the transistor Q1 of the differential transistor circuit 11, and the resistor R5
Connected through. Further, the collector of the transistor Q5 of the second logical amplitude amplifier 63 is not directly connected to the collector of the transistor Q2 of the differential transistor circuit 11, but is connected via a resistor R6.

By adopting such a circuit configuration,
When the power supply voltage rises (or falls) and the base potential of transistor Q3 or Q5 rises (or falls), the current flowing through resistor R5 or R6 increases (or decreases), and the amount of voltage drop by resistor R5 or R6 Increases (or decreases). Therefore, the collector potential of the transistor Q3 or Q5 decreases (or increases), the voltage between the collector and the emitter decreases (or increases), and the collector current decreases (or increases), so that the base potential decreases (or increases). As a result, a feedback effect is obtained. Therefore, even if the power supply voltage fluctuates, a fluctuation in the value of the current flowing through the transistor Q4 or Q6, which is a current source, can be suppressed to a small value, so that a stable operation can be realized.

FIG. 7 is a diagram showing a configuration of a level conversion circuit according to the third embodiment of the present invention. FIG.
FIG. 8 is a diagram showing an example of waveforms at nodes K and L of the level conversion circuit shown in FIG. FIG. 9 is a diagram showing a waveform example at nodes OUT and OUTB of the level conversion circuit shown in FIG.

The configuration of the level conversion circuit according to the third embodiment shown in FIG. 7 corresponds to the configuration of the level conversion circuit according to the first embodiment shown in FIG. In the configuration of FIG. 7, the description of the same parts as those of the configuration of FIG. 1 is omitted. 7 differs from FIG. 1 in that the other end of the resistor R3, one end of which is connected to the collector of the transistor Q4 of the first logical amplitude amplifier circuit 82, is not directly connected to the voltage source VDD, but is connected via the resistor R7. Connected. The other end of the resistor R4, one end of which is connected to the collector of the transistor Q6 of the second logical amplitude amplifier 83, is not directly connected to the voltage source VDD, but is connected via a resistor R7. In such a circuit configuration, the value of the resistor R7 is set so that the voltage drop due to the resistor R7 becomes equal to the voltage between the collector and the emitter of the transistors Q4 and Q6.

The operation of the level conversion circuit shown in FIG. 7 when a 1V power supply is used will be described. As shown in FIG. 8, the first CM
The voltage of the node K serving as the input of the OS inverter 14 and the voltage of the node L serving as the input of the second CMOS inverter 15 are such that the high level is lower than the power supply voltage by a voltage drop due to the resistor R7, and the low level is the transistor Q4. Or, it becomes the collector-emitter voltage of Q6. As a result, the cross point between the voltage at the node K and the voltage at the node L is １ ／ (0. 0) of the power supply voltage, as apparent from comparison with the voltages at the nodes C and D shown in FIG.
5V).

In the level conversion circuit shown in FIG.
The area of the Pch MOSFET, which is inferior to that of the MOSFET, is greatly increased, and the Nch MOSFET and Pc constituting the first and second CMOS inverters 14 and 15 are increased.
The balance of the capability with the hMOSFET must be adjusted. This is because not only a CMOS level full-swing output whose center of amplitude is 電源 of the power supply voltage as shown in FIG. This is because the time and the fall time are greatly different.

However, according to the circuit configuration of the third embodiment shown in FIG. 7, the area of the PchMOSFETs constituting the first and second CMOS inverters 14 and 15 is made much larger than that of the NchMOSFET. Without any difference, as shown in FIG.
/ 2, the rise time and fall time are equal C
MOS level full swing output can be obtained.

FIG. 10 is a diagram showing a configuration of a level conversion circuit according to a fourth embodiment of the present invention. The configuration of the level conversion circuit according to the fourth embodiment shown in FIG. 10 corresponds to the configuration of the level conversion circuit according to the third embodiment shown in FIG. In the configuration of FIG. 10, the description of the same parts as those of the configuration of FIG. 7 is omitted. 10 is different from FIG. 7 in that the collector of the transistor Q3 of the first logical amplitude amplifier circuit 92 is different from the differential transistor circuit 1 in FIG.
1 without being directly connected to the collector of the transistor Q1,
It is connected via a resistor R5. Further, the collector of the transistor Q5 of the second logic amplitude amplifier circuit 93 is not directly connected to the collector of the transistor Q2 of the differential transistor circuit 11, but is connected via a resistor R6.

The operation of the level conversion circuit shown in FIG.
Since the level conversion circuit shown in FIG. 6 and the level conversion circuit shown in FIG. 7 can be easily explained, the description is omitted.

[0035]

As described above, the level conversion circuit of the present invention has two outputs (nodes A and B) of a differential transistor circuit receiving two inputs at the ECL level.
Are input to the first or second CMOS inverters via the first or second logical amplitude amplifier circuits, respectively, to operate at a low voltage of about 1 V, thereby reducing the input offset voltage of the ECL level input signal. And differential logic CM
This has the effect that an OS level signal output can be obtained.

The node A or node B, which is the output of the differential transistor circuit, is not directly connected to the transistor Q3 or Q5 but is connected via the resistor R5 or R6, so that a feedback effect is obtained and the power supply voltage is obtained. Has the effect that the variation in the value of the current flowing through the transistor Q4 or Q6, which is the current source, is suppressed to a small value, and a stable operation can be realized.

Further, a resistor R3 having one end connected to the collector of the transistor Q4 of the first logical amplitude amplifier circuit.
And the transistor Q6 of the second logical amplitude amplifier circuit
Of the first and second CMOS inverters, that is, by connecting the other end of the resistor R4, one end of which is connected to the collector of the first and second CMOS inverters, via the resistor R7 instead of directly connecting to the voltage source. The cross point between the voltage at the node K and the voltage at the node L can be reduced to 電源 of the power supply voltage.
There is no need to increase the area ratio between the lower (Pch) and the higher (Nch) MOSFETs of the MOSFETs constituting the inverter, and the element area can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention;

FIG. 2 shows inputs IN, IN of the level conversion circuit shown in FIG.
The figure which shows the example of a waveform in B

FIG. 3 is a diagram showing a waveform example at nodes A and B of the level conversion circuit shown in FIG. 1;

FIG. 4 is a diagram showing an example of waveforms at nodes C and D of the level conversion circuit shown in FIG. 1;

FIG. 5 illustrates nodes OUT and OUT of the level conversion circuit illustrated in FIG.
The figure which shows the example of a waveform in OUTB

FIG. 6 is a diagram illustrating a configuration of a level conversion circuit according to a second embodiment of the present invention;

FIG. 7 is a diagram illustrating a configuration of a level conversion circuit according to a third embodiment of the present invention;

FIG. 8 is a diagram showing a waveform example at nodes K and L of the level conversion circuit shown in FIG. 7;

FIG. 9 shows nodes OUT, OUT of the level conversion circuit shown in FIG.
The figure which shows the example of a waveform in OUTB

FIG. 10 is a diagram showing a configuration of a level conversion circuit according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of an example of a conventional level conversion circuit;

FIG. 12 shows the inputs IN, IN of the level conversion circuit shown in FIG. 11;
The figure which shows the example of a waveform in INB

13 is a diagram showing an example of a waveform at a node E of the level conversion circuit shown in FIG. 11;

14 is a diagram showing an example of a waveform at a node F of the level conversion circuit shown in FIG. 11;

FIG. 15 shows a node OU of the level conversion circuit shown in FIG. 11;
The figure which shows the example of a waveform in T

FIG. 16 is a diagram showing a configuration of another example of a conventional level conversion circuit.

[Explanation of symbols]

 11, 71, 121 Differential transistor circuit 12, 62, 82, 92 First logical amplitude amplifier circuit 13, 63, 83, 93 Second logical amplitude amplifier circuit 14 First CMOS inverter 15 Second CMOS inverter 72 Logical amplitude amplifier 73 CMOS inverter 122 First level shift circuit 123 Second level shift circuit 124 First CMOS output circuit 125 Second CMOS output circuit IN, INB Input terminal OUT, OUTB Output terminal IDD1, IDD2, IDD3 Current source VDD Voltage source R1 to R7 Resistance Q1 to Q6 Bipolar transistor MP1, MP2 PchMOSFET MN1, MN2 NchMOSFET

Claims (4)

(57) [Claims] 1. A differential transistor circuit for inputting an ECL level logical amplitude signal, and a first logic for receiving a first output signal of the differential transistor circuit and amplifying a logical amplitude of the first output signal An amplitude amplifying circuit, a second logical amplitude amplifying circuit for receiving a second output signal of the differential transistor circuit and amplifying a logical amplitude of the second output signal, and a second logical amplitude amplifying circuit of the first logical amplitude amplifying circuit. A first CMOS inverter which inputs the output signal of No. 3 and outputs a CMOS level signal, and a second which inputs the fourth output signal of the second logical amplitude amplifier circuit and outputs a CMOS level signal A CMOS inverter, and an output signal of the first CMOS inverter and the second CM
The output signal of the OS inverter has a differential logic,
Level conversion circuit. 2. A differential transistor circuit comprising: a first transistor and a second transistor forming a differential pair receiving an ECL level input signal; a first resistor and a second resistor serving as load resistors; A current source having one end grounded, the first transistor having a collector connected to one end of the first resistor, a base connected to a first ECL level input signal, and an emitter connected to the first ECL level input signal. The first resistor is connected to the other end of the current source, one end is connected to the collector of the first transistor, the other end is connected to the voltage source, and the collector potential of the first transistor is the The second transistor has a collector connected to one end of the second resistor, a base connected to an input signal at a second ECL level, and an emitter connected to the other end of the current source. Connected, the second A resistor having one end connected to the collector of the second transistor and the other end connected to the voltage source; the collector potential of the second transistor being the second output signal; An amplitude amplifying circuit having a third transistor, a fourth transistor, and a third resistor, wherein the third transistor has a collector and a base connected to the first transistor;
The fourth transistor has a collector connected to one end of the third resistor, a base connected to the base of the third transistor, and an emitter grounded. The third resistor has one end connected to the collector of the fourth transistor, the other end connected to the voltage source, and the collector potential of the fourth transistor is the third output signal; The second logic amplitude amplifier circuit has a fifth transistor, a sixth transistor, and a fourth resistor, and the fifth transistor has a collector and a base connected to the second transistor.
The sixth transistor has a collector connected to one end of the fourth resistor, a base connected to the base of the fifth transistor, and an emitter grounded. The fourth resistor has one end connected to the collector of the sixth transistor, the other end connected to the voltage source, and the collector potential of the sixth transistor is the fourth output signal. The level conversion circuit according to claim 1. 3. The first logic amplitude amplifier circuit has a fifth resistor, the second logic amplitude amplifier circuit has a sixth resistor, and the third transistor has a collector connected to the third resistor. 5, the base is connected to the collector of the first transistor, the emitter is grounded, and the other end of the fifth resistor is connected to the collector of the first transistor; The fifth transistor has a collector connected to one end of the sixth resistor, a base connected to the collector of the second transistor, an emitter grounded, and another end connected to the second resistor. 3. The level conversion circuit according to claim 2, wherein the level conversion circuit is connected to a collector of the transistor. 4. The third resistor having a seventh resistor, one end of which is connected to the collector of the fourth transistor, the other end of which is connected to one end of the seventh resistor, The other end of the fourth resistor having one end connected to the collector of the transistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the voltage source. The level conversion circuit according to claim 2.