JP2787136B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

According to the present invention, any one of a plurality of n first logic signals having a level which takes a first logic amplitude, which has a relationship in which one of them is logically inverted with respect to all others, is obtained by combining the plurality of n first logic signals with each other. Corresponding to the first logic signal, any one of which has a relationship that the logic is inverted with respect to all the others, but a plurality of n signals each having a level having a logic amplitude larger than the first logic amplitude A level conversion circuit that converts a decoder output signal having a level with a relatively small logic amplitude output from a decoder configured using a bipolar transistor, using a MOS transistor. It is suitable to be applied to a case where the memory circuit is stored by being converted into a logic signal having a level having a logic amplitude larger than that of the decoder output signal and inputted thereto, which is suitable for the memory circuit. On the bell conversion circuit.

[Prior art]

Conventionally, a level conversion circuit described below with reference to FIG. 18 has been proposed. That is, one is but logically inverted relative to all other, both a plurality of n first logic having a first logic amplitude V take _a high potential level V _Ha and the low potential level V _La having a signal a _1, a ₂ ......... plurality n input terminals T ₁ to a _n and inputs respectively, T ₂ ......... T _n. Although any one in correspondence with a plurality of n first logic signal A _1, A ₂ ......... A _n are logically inverted with respect to every other, both the first logic amplitude V _a ... _Bn each having a plurality of n second logic signals B ₁ , B _2, ..., B _n having a high potential level V _Hb and a low potential level V _Lb having a second logic amplitude _Vb larger than having n output terminals _{K 1, K 2 ......... K n} . Further, both the p-channel MIS field-effect transistor M1 and the n-channel MIS field-effect transistor M1 having the drain connected to the drain of the p-channel MIS field-effect transistor M1
A plurality of n inverter IN _1, IN ₂ ......... IN _n and a S field effect transistors M2, and an inverter I
N ₁ , IN ₂ ... IN _n p-channel MIS field-effect transistors M1 have a source connected to a first power supply terminal E1 to which a common first voltage V ₁ (normally 0 V, which is a ground voltage) is applied. It is connected to, and the drain of inverter iN _1, iN ₂ ......... iN _n of n-channel type MIS field effect transistor M2,
A second voltage V ₁ (for example, −3.0) that is lower than the voltage V ₁ applied to the first power supply terminal E1 in common with them as a reference.
V) is connected to a second power supply terminal E2 to which a p-channel MIS of the inverters IN ₁ , IN ₂ ... IN _n is connected.
The gate of the field effect transistors M1 and n-channel type MIS field effect transistor M2 is common to them, are connected to input terminals T _1, T ₂ ......... TR _n described above, also, the inverter IN _1, IN ₂ ... …… IN _n p-channel MIS
An inverter circuit INC which drain connection midpoint of the field effect transistors M1 and n-channel type MIS field effect transistor M2 is connected to the output terminal K _1, K ₂ ......... K _n described above. The above is the configuration of the conventionally proposed level conversion circuit. According to the conventional level conversion circuit having such a configuration, the first logic signal A _i given to the input terminal T _i (i = 1, 2,..., N) is given to the first power supply terminal E1. The first
Takes a high potential level V _Ha having a level (0 V) substantially equal to the voltage V ₁ of the inverter IN _{i of the} inverter circuit INC.
P-channel MIS field-effect transistor M1 exhibits relatively high conductivity between the source and the drain, and the n-channel MIS field-effect transistor M2 of the inverter IN _i
There exhibit relatively high conductivity between the source and the drain, or Thus, the output terminal K _i, the second logic signal B _i is approximately equal to the second voltage applied to the second power supply terminal E2 V2 or the voltage V ₁ and the second low-potential level is in the middle of the voltage has the level close to the second voltage V ₂ and the voltage V ₂
V _Lb. The first logic signal A _i applied to the input terminal T _i is,
The first power supply terminal and the first voltages V ₁ applied to the E1 second level close to just intermediate voltage of the second voltage V ₂ applied to the power supply terminal E2 (e.g., -1.6 V) low have a Potential level
When V _Ha is taken, the p-channel MIS field-effect transistor M1 of the inverter IN _i of the inverter circuit INC exhibits relatively low conductivity between the source and the drain, and the n-channel MIS field-effect transistor M2 of the inverter IN _i There exhibit relatively low conductivity between the source and the drain, and therefore, the output terminal K _i, the second logic signal B _i is obtained in the high potential level V _Hb. And in this case, the inverter circuit I
If the p-channel MIS field-effect transistor M1 in the NC inverter IN _i has a relatively high transconductance, and thus a relatively wide channel width, the p-channel MIS field-effect transistor M1 can be sufficiently connected between the source and the drain. since exhibiting high conductivity, high potential level V _Lb of the second logic signal B _i obtained at the output terminal K _i is first
The first voltages V ₁ applied to the power supply terminal E1 and obtain a substantially equal level (≒ V). Therefore, according to the conventional level conversion circuit shown in FIG. 18, any one has the relationships that are logically inverted with respect to every other, both the first logic amplitude V _a (0V-1.6V =
1.6V) a plurality of n first logic signals having a level taking
A ₁ , A ₂ ... _An are represented by a plurality of n first logic signals.
A _1, A ₂ ......... A _n one corresponding to it has a relationship that is logically inverted with respect to every other, both large logic amplitude V _b than the first logic amplitude V _a (Almost 0V-3.0V = 3.0V
Or a value having a value close to that) has a function of level conversion into a plurality of n second logic signals B1, B2,.

[Problems to be solved by the invention]

However, in the conventional level conversion circuit shown in FIG. 18, when the second logic signal B _i is obtained by taking the high potential level V _Hb, the high potential level V _Hb is the first power supply terminal E1
Substantially equal level as the first voltages V ₁ applied to the (≒ 0V)
In order to obtain the above, as described above, the inverter circuit
Since the p-channel MIS field-effect transistor M1 in the INC inverter IN _i needs to have a relatively wide channel width, the p-channel MIS field-effect transistor M1 has a relatively small gate capacitance. Therefore, the level conversion function described above cannot be obtained at a sufficiently high speed, and
It has a disadvantage that it involves relatively large power consumption. Therefore, the present invention proposes a novel level conversion circuit that does not have the above-mentioned disadvantages.

[Means for Solving the Problems]

The level conversion circuit according to the first invention of the present application has a relationship in which one of them is logically inverted with respect to all the others as in the case of the conventional level conversion circuit described above with reference to FIG. a plurality of n input terminals T _1, T ₂ ......... T _n which respectively input a plurality of n first logic signal a ₁ of, a ₂ ......... a _n having a level which takes a first logic amplitude , One of which has a logically inverted relationship with respect to all others, but a plurality of n second logics each having a level having a second logic amplitude larger than the first logic amplitude. signal
B ₁ , B ₂ ……… A plurality of n output terminals for outputting B _n respectively
And a _{K 1, K 2 ......... K n} . However, the level conversion circuit according to the first invention of the present application is a p-channel MIS field-effect transistor and an n-channel MI-channel transistor having a drain connected to the drain of the p-channel MIS field-effect transistor.
A plurality of n inverter IN _1, IN ₂ ......... IN _n and a S field effect transistors, the inverter IN _1, IN ₂
The source of the p-channel type MIS field effect transistor of ......... IN _n is connected to a common first power supply terminal thereof, the n-channel type MIS field of the inverter IN _1, IN ₂ ......... IN _n The sources of the effect transistors are connected to a second power supply terminal to which a voltage lower than the voltage supplied to the first power supply terminal common to them is applied, and the inverters IN ₁ , IN ₂ ... the gate of the p-channel type MIS field effect transistor and the n-channel type MIS field effect transistor of the iN _n is common to them, the input terminals T _1, T ₂ ......... T _n inverter circuits are respectively connected to the And a plurality of n amplifier circuits AM1 and AM2 both having an npn-type bipolar transistor for amplification and a load resistor having one end connected to the collector of the pnp-type bipolar transistor for amplification. ……… have AM _n
The other ends of the load resistors of the amplifier circuits AM ₁ , AM ₂ ... AM _n are commonly connected to the first power supply terminal,
The amplifiers of the amplifier circuits AM ₁ , AM ₂ ... AM _n are connected to the emitters of the npn-type bipolar transistors for amplification through a constant current circuit common to the emitters based on the voltage supplied to the first power supply terminal. is lower than the voltage applied to the power supply terminal is connected to a third power supply terminal supplied, the amplifier circuit AM _1, AM ₂ ......... base the inverter iN ₁ for amplification npn-type bipolar transistor AM _n, IN ₂ ……… IN _n
The p-channel MIS field-effect transistor and n
The amplifiers AM ₁ , AM ₂ are connected to the connection middle points of the drains of the channel type MIS field-effect transistors, respectively.
... A current switching type in which the connection point between the collector of the npn-type bipolar transistor for amplification of AM _n and the load resistance or the division point of the load resistance is connected to the output terminals K ₁ , K 2. And an amplifier circuit. According to a second aspect of the present invention, a level conversion circuit comprises:
In the level conversion circuit according to the first invention of the present application, the p-channel MIS field-effect transistor in each of the inverters IN ₁ , IN ₂ ... IN _n of the inverter circuit is replaced by a pnp bipolar transistor for inversion. In the level conversion circuit according to the first invention, the "p-channel MIS field-effect transistor" is replaced with a "pnp bipolar transistor for inversion."
"The drain of the p-channel MIS field-effect transistor" is "the collector of the pnp bipolar transistor for inversion", and the "source of the p-channel MIS field-effect transistor" is "emitter of the pnp bipolar transistor for inversion". The "gate of the p-channel MIS field-effect transistor" is replaced with the "base of a pnp bipolar transistor for inversion". Further, in the level conversion circuit according to the third invention of the present application, the n-channel MIS field-effect transistor in each of the inverters IN ₁ , IN ₂ ... IN _n of the inverter circuit in the level conversion circuit according to the first invention of the present application. The n-channel type in the level conversion circuit according to the first invention of the present application is replaced by the first load resistance.
"MIS field-effect transistor" as "first load resistance"
"Drain of n-channel MIS field-effect transistor" is referred to as "one end of the first load resistor"
The “source of the MIS field-effect transistor” is “the other end of the first load resistor”, and the “gate of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor” is “the gate of the p-channel MIS field-effect transistor”. And "the drain connection point of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor" to "the connection point between the drain of the p-channel MIS field-effect transistor and the first load resistance or the second connection point." Of the load resistance of the current switching type amplifier circuit and the "second load resistance" of the current switching type amplifier circuit. Furthermore, the present level conversion circuit according to a fourth invention, in the level converting circuit according to the present 1st invention, p-channel type MIS field effect transistor in each of the inverter IN _1, IN ₂ ......... IN _n of the inverter circuit Is replaced by a pnp bipolar transistor for inversion in the same manner as in the case of the level conversion circuit according to the second invention of the present application, and the n-channel MIS field-effect transistor is similar to the case of the level conversion circuit according to the third invention of the present application. Therefore, in the level conversion circuit according to the first invention of the present application, the “p-channel MIS field-effect transistor” is replaced by the “pnp-type bipolar transistor for inversion” and the “p-channel MIS field-effect transistor”. Transistor drain to pnp for invert
The collector of a p-type bipolar transistor and the source of a p-channel MIS field-effect transistor are called the emitter of a pnp bipolar transistor for inversion.
"Gate of p-channel MIS field-effect transistor"
Is read as "base of pnp bipolar transistor for inversion", and "n-channel MIS field-effect transistor" is referred to as "first load resistance" and "drain of n-channel MIS field-effect transistor" is referred to as " 1, one end of the load resistance "," the source of the n-channel MIS field-effect transistor "as" the other end of the first load resistance ", and" the other end of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor ". Gate"
"The gate of the p-channel MIS field-effect transistor" and "the midpoint of the connection between the drains of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor" The configuration is such that the connection point with the first load resistor or the division point of the second load resistor ”and the“ load resistance ”of the current switching type amplifier circuit are replaced with“ the second load resistor ”. Further, the level conversion circuit according to the fifth invention of the present application is:
In the level conversion circuit according to the first invention or the second invention, the inverters IN ₁ , IN ₂ ...
, IN _n , a diode is connected in parallel with the n-channel MIS field-effect transistor. Further, the level conversion circuit according to the sixth invention of the present application is the same as the level conversion circuit according to the fifth invention of the present application, in the level conversion circuit according to the third invention or the fourth invention of the present application. Inverter I
In each of N ₁ , IN ₂ ... IN _n , a diode is connected in parallel with the first load resistance. Also, the level conversion circuit according to the seventh invention of the present application is:
In the level conversion circuit according to the first invention or the second invention of the present application, the amplifier circuits AM ₁ , AM ₂ ...
At each of AM _n , in parallel with its load resistance,
Compensating npn-type bipolar transistors are connected, and the bases of the compensating npn-type bipolar transistors of the amplifier circuits AM ₁ , AM ₂ ... AM _n are connected to the input terminals T ₁ , T ₂ ,.
.. Are connected to T _n respectively. Further, the level conversion circuit according to the eighth invention of the present application is the same as the level conversion circuit according to the seventh invention of the present application, in the level conversion circuit according to the third invention or the fourth invention of the present application. Amplifier circuits AM ₁ and A
In each of the M ₂ ......... AM _n, in parallel with its said second load resistor, compensating npn-type bipolar transistor is connected, and, for compensating the amplifier circuit AM _1, AM ₂ ......... AM _n The input terminals T ₁ , T _2, ..., T _n are connected to the base of the npn-type bipolar transistor, respectively.

[Action / Effect]

According to the level conversion circuit of the first invention of the present application,
When the first logic signal A _{i applied} to the input terminal T _i (i = 1, 2,... N) assumes a high potential level having a level substantially equal to the voltage applied to the first power supply terminal, 18 in accordance with the conventional level conversion circuit described above in Fig exhibit relatively low conductivity p-channel type MIS field effect transistor of the inverter iN _i of the inverter circuit INC is between the source and drain, the inverter iN _i N-channel MIS field-effect transistor exhibits relatively high conductivity between the source and the drain, so that the connection point between the drains of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor of the inverter IN _i Is substantially equal to the voltage applied to the second power supply terminal, or the voltage applied to the first power supply terminal and the voltage applied to the second power supply terminal. There is an intermediate voltage is obtained at a low potential level having a level close to the voltage applied to the second power supply terminal. The first logic signal A _i applied to the input terminal T _i is,
When a low potential level having a level close to a voltage exactly intermediate between the voltage supplied to the first power supply terminal and the voltage supplied to the second power supply terminal is taken, the case of the conventional level conversion circuit described above with reference to FIG. according to exhibit relatively high conductivity p-channel type MIS field effect transistor of the inverter iN _i of the inverter circuit INC is between the source and the drain, also, n channel type MIS field effect transistor source and drain of the inverter iN _i exhibit relatively low conductivity between, Therefore, the logical signal from the connection point between the drain of the p-channel type MIS field effect transistor and the n-channel type MIS field effect transistor of the inverter iN _i are obtained in a high potential level. Furthermore, when the drain logic signals obtained as described above from the connection point of the p-channel type MIS field effect transistor and the n-channel type MIS field effect transistor of the inverter IN _i takes a low potential level, the current switching換形amplifier circuit amplifying npn type bipolar transistor of the amplifier circuit AM _i can not shed little current to the load resistor, Therefore, the output terminal K _i, the second logic signal B _i is obtained at a high potential level. Furthermore, when the drain logic signals obtained as described above from the connection point of the p-channel type MIS field effect transistor and the n-channel type MIS field effect transistor of the inverter IN _i takes a high potential level, the current switching換形amplifier circuit amplifying npn type bipolar transistor of the amplifier circuit AM _i is flowing relatively large current to the load resistor, Therefore, the output terminal K _i, the second logic signal B _i is obtained at a low potential level. Therefore, as in the case of the conventional level conversion circuit described above with reference to FIG. 18, any one of them has a logically inverted relationship with respect to all the others, but both levels take the first logical amplitude Va. Having a plurality of n first logic signals A ₁ , A ₂ ...
.. _An are represented by a plurality of n first logic signals A ₁ , A _2.
Although any one corresponds to A _n have the relationship that is logically inverted with respect to every other, the plurality of n having a level taking both large logic amplitude V _b than the first logic amplitude V _a Second
Have the function of level conversion into the logical signals B ₁ , B ₂ ... _Bn . However, when the level conversion circuit according to the present 1st invention, when the first logic signal A _i is obtained by taking the high potential level, p-channel type MIS field effect transistor and the n-channel in the inverter IN _i of the inverter circuit Even if the high potential level of the logic signal obtained from the connection middle point of the drain of the type MIS field effect transistor does not have a level substantially equal to the voltage applied to the first power supply terminal, the second logic signal B _i , p-channel inverter iN _i-type MIS field effect transistor and the n-channel type MIS
Since the second logic signal Bi is obtained based on the logic signal obtained from the connection middle point of the drain of the field effect transistor, the level of the second logic signal _Bi is substantially equal to the voltage applied to the second power supply terminal or the first voltage. At a low potential level which is intermediate between the second voltage and the second voltage but has a level close to the second voltage. Further, when the first logic signal A _i is obtained by taking the low potential level, p in the inverter IN _i of the inverter circuit
The low potential level of the logic signal obtained from the connection point between the drains of the channel type MIS field effect transistor and the n channel type MIS field effect transistor is substantially equal to or close to the voltage applied to the second power supply terminal. Even if they do not, the second logic signal B _i is based on the logic signal obtained from the connection point between the drains of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor of the inverter IN _i. As a result, the second logic signal _Bi is obtained at a high potential level having a level substantially equal to the voltage applied to the first power supply terminal. Therefore, the p-channel type MIS in the inverter IN _i
Since the field-effect transistor does not need to have a relatively wide channel width, the p-channel MIS field-effect transistor can have only a relatively small gate capacitance. Can be obtained at a higher speed than in the case of the conventional level conversion circuit described above with reference to FIG. 18, and the power consumption is smaller than in the case of the conventional level conversion circuit described above with reference to FIG. According to the level conversion circuit of the second invention of the present application, in the level conversion circuit of the first invention of the present application, the inverters IN ₁ , IN ₂ ,.
Except that the p-channel MIS field-effect transistor in _n is replaced with a pnp bipolar transistor for inversion, it has the same configuration as the level conversion circuit according to the first invention of the present application, and therefore detailed description is omitted. Thus, excellent operational effects similar to those of the level conversion circuit according to the first invention of the present application can be obtained. Further, according to the level conversion circuit according to the third invention of the present application, in the level conversion circuit according to the first invention of the present application, the inverters IN ₁ , IN ₂ ...
Except that the n-channel MIS field-effect transistor at IN _n is replaced with a first load resistor, it has the same configuration as that of the level conversion circuit according to the first invention of the present application, and therefore detailed description is omitted. Thus, excellent operational effects similar to those of the level conversion circuit according to the first invention of the present application can be obtained. Further, according to the level conversion circuit of the fourth invention of the present application, in the level conversion circuit of the first invention of the present application, the inverters IN ₁ , IN ₂ ,.
the p-channel MIS field-effect transistor in _n is replaced with a pnp bipolar transistor for inversion,
Except that the n-channel MIS field-effect transistor is replaced with a first load resistor, it has the same configuration as the level conversion circuit according to the first invention of the present application. An excellent operation and effect similar to the case of the level conversion circuit according to the first invention can be obtained. Further, according to the level conversion circuit according to the fifth invention of the present application, in the level conversion circuit according to the first invention of the present application or the second invention of the present application, _n in the inverters IN ₁ , IN ₂ ... IN _n of the inverter circuit. Except that a diode is connected in parallel with the channel type MIS field-effect transistor, it has the same configuration as that of the level conversion circuit according to the first invention or the second invention of the present application, and the inverter IN _i The diode connected in parallel with the n-channel MIS field-effect transistor has uneven characteristics of the n-channel MIS field-effect transistor, so that the voltage between the drain and the source of the n-channel MIS field-effect transistor increases. Even if it tries, since the voltage between both ends is kept constant to the voltage drop of the diode, the first generation of this application Or the similar effects as described above in the level conversion circuit according to the second aspect th invention is obtained, the level switching functions described above can be obtained more stably. Further, according to the level converting circuit according to the present sixth invention, in the level converting circuit according to the present third invention or the present fourth invention, in the inverter IN _1, IN ₂ ......... IN _n of the inverter circuit Except that a diode is connected in parallel with the first load resistance,
Th has invention or present fourth configuration similar to that of the level conversion circuit according to the invention, and, the first load resistor and a diode connected in parallel in the inverter IN _i is the first load resistor resistor Even if the voltage across the first load resistor becomes high due to the uneven value,
Since the voltage between both ends can be kept constant at the voltage drop of the diode, the same function and effect as described above can be obtained with the level conversion circuit according to the third invention or the fourth invention of the present application. The conversion function can be obtained more stably. Further, according to the level conversion circuit according to the seventh invention of the present application, in the level conversion circuit according to the first invention of the present application or the second invention of the present application, the amplification circuits AM ₁ , AM ₂ of the current switching type amplification circuit are provided. ... except that a compensating npn-type bipolar transistor is connected in parallel with the load resistance at AM _n,
Has the same configuration as the level conversion circuit according to the second invention,
The compensating npn-type bipolar transistor connected in parallel with the load resistance of the amplifier circuit AM _i and the amplifying npn-type bipolar transistor operate in an inverse relationship, and the compensating npn-type bipolar transistor has an input terminal T. _i
Since it operates by first logic signal A _i from is directly supplied, amplifying npn type bipolar transistor, operates in the fast rise time compared to the case having no compensating npn bipolar transistor Therefore, the same effect as described above can be obtained with the level conversion circuit according to the first invention or the second invention, and the level conversion function can be obtained at a higher speed.

Embodiment 1 Next, a first embodiment of a level conversion circuit according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 18 are given the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the present invention shown in FIG. 1 has the same configuration as that of the conventional level conversion circuit described above with reference to FIG. 18, except for the following. That is, a plurality of n amplifying circuits AM ₁ , AM ₂ ... AM _n each having an amplifying npn-type bipolar transistor Q and a load resistor having one end connected to the collector of the amplifying npn-type bipolar transistor Q are provided. And amplifier circuit A
M ₁ , AM ₂ ... The other end of the load resistor R of AMI _n is commonly connected to a first power supply terminal E, and the amplifier circuit AM
₁ , AM ₂ ... The emitter of the npn amplifying bipolar transistor Q of AM _n is connected to the second power supply terminal with reference to the voltage supplied to the first power supply terminal E1 through the common constant current circuit H. voltage lower than the voltage applied is connected to a third power supply terminal E3 given to further amplifier AM _1, AM ₂ ......... AM _n base In'nata iN ₁ for amplification npn-type bipolar transistor Q of IN ₂ ... IN _n are respectively connected to the drain connection points of the p-channel MIS field-effect transistor M1 and the n-channel MIS field-effect transistor M2 of IN _n , and the amplifier circuits AM ₁ , AM _2.
division point of connection point or load resistance R of the _n collector of the amplifying npn-type bipolar transistor Q of the load resistor R (the former in the figure), respectively connected to the output terminal K _1, K ₂ ......... K _n Current switching type amplifier circuit AMC. The above is the configuration of the embodiment of the level conversion circuit according to the present invention. According to the level conversion circuit of the present invention having such a configuration, the first logic signal A _i given to the input terminal T _i (i = 1, 2,..., N) is connected to the first power supply terminal E1. when taking the high potential level VHa having approximately equal level voltage applied and, FIG. 18 in according to the conventional level conversion circuit described above, the inverter circuit INC inverter iN _i p-channel type MIS field effect transistor of M1 Exhibit relatively low conductivity between the source and the drain, and
IN _i n-channel type MIS field effect transistor M2 exhibits a relatively high conductivity between the source and the drain of this reason, p-channel type MIS field effect transistor and the n-channel type MIS field effect transistor of the inverter IN _i M2
From the middle point of the connection of the drain of the second power supply terminal
Approximately equal to or first and second voltages V ₁ applied to the E2
Nearby is the voltage V ₂ applied to the second power supply terminal E2 at first given to the power supply terminal E1 of the voltage V1 to the intermediate voltage between the second voltage V ₂ applied to the second power supply terminal E2 Obtained at a low potential level having a level. The first logic signal A _i applied to the input terminal T _i is,
When taking a low potential level VLa having a level close to a voltage just intermediate between the first voltage V1 applied to the first power supply terminal E1 and the second voltage V2 applied to the second power supply terminal E2,
According to the conventional level conversion circuit described above with reference to FIG.
P-channel MI of inverter IN _i of inverter circuit INC
Exhibit relatively high conductivity S field effect transistor M1 is between the source and the drain, also, exhibit a relatively low conductivity n-channel type MIS field effect transistor M2 of the inverter IN _i is between the source and the drain, and therefore, logic signal from a connection midpoint of the drain of the inverter iN _i of p-channel type MIS field effect transistor M1 and the n-channel type MIS field effect transistor M2 is obtained at a high potential level. Furthermore, when a logical signal obtained as described above from the connection point of the drain of the inverter IN _i of p-channel type MIS field effect transistor M1 and the n-channel type MIS field effect transistor M2 takes a low potential level, current switching換形amplification little current flows in the amplifier circuit AM _i amplifying npn-type bipolar transistor Q is the load resistance R of circuit AMC, Therefore, the output terminal K _i, the second logic signal B _i is obtained at a high potential level VHb . Further, when a logical signal obtained as described above from the connection point of the drain of the inverter IN _i of p-channel type MIS field effect transistor M1 and the n-channel type MIS field effect transistor M2 takes a high potential level, current switching換形amplification flowing amplifier circuit AM _i amplifying npn-type bipolar transistor Q is relatively large current to the load resistance of the circuit AMC, Therefore, the output terminal K _i, a second logic signal Bi is low potential level V
Obtained in Lb. Accordingly, as in the case of the conventional level conversion circuit described above with reference to FIG. 18, any one has a logically inverted relationship with respect to all the others, but both have the first logical amplitude V _a (0V
-1.6 V = 1.6V a plurality of n of the first logic signal A _1, A ₂ ......... A _n having a level taking), the plurality of n first logic signal A _1, A ₂ ...... ... have a relationship that any one against a _n are logically inverted with respect to every other, both the first
Has a function of level conversion to a plurality of n second logic signals B _1, B ₂ ......... B _n having a level taking the logical amplitude V _a large logic amplitude V _b relative to the. However, in the case of the level conversion circuit according to the present invention shown in FIG. 1, when the first logic signal A _i is obtained at the high potential level VHa, the inverter IN _{i of the} inverter circuit INC is used.
The high potential level of the logic signal obtained from the connection point of the drains of the p-channel MIS field-effect transistor M1 and the n-channel MIS field-effect transistor M2 in
Need not have a substantially equal level as the first voltage V1 applied to the first power supply terminal E1, a second logic signal B _i is, p-channel type MIS field effect transistor of the inverter IN _i
M1 and n-channel type since also obtained Ki not a preparative to a logic signal derived from the drain of the connection midpoint of the MIS field-effect transistors M2, first the second logic signal B _i is applied to the second power supply terminal E2 2 At a low potential level VLb having a level close to the voltage V2. Further, when the first logic signal A _i is obtained by taking the low potential level VLa, the inverter circuit p-channel type MIS field effect transistors M1 and n in the inverter IN _i of INC
The low potential level of the logic signal obtained from the connection point of the drain of the channel type MIS field-effect transistor M2 is the second level.
Be a second voltage applied to the power supply terminal E2 V2 not have a substantially equal to or a level close to its second voltage V2, the second logic signal B _i is, p-channel type inverter IN _i MIS field-effect transistor M1 and n-channel type MIS
Since also obtained Ki not a preparative to a logic signal derived from a connection midpoint of the drain of the field effect transistors M2, substantially equal to the first voltage V1 that the second logic signal B _i is applied to the first power supply terminal E1 Obtained at a high potential level having the level VHb. Therefore, the p-channel type MIS in the inverter IN _i
Since the field effect transistor M1 does not need to have a relatively wide channel width, its p-channel type MIS
The field effect transistor M1 can have only a relatively small gate capacitance, so that the level conversion function described above can be obtained at a higher speed than in the case of the conventional level conversion circuit described above with reference to FIG. . This is the fifth
In the figure, the delay time τ of the first logic signal Ai with respect to the logic signal Va of the first logic signal Ai with respect to the first logic signal Ai of the second logic signal Bi is compared with the case of the conventional level conversion circuit described above with reference to FIG.
It will be clear from showing the relationship. Further, for the above-described reason, the power consumption is smaller than that of the conventional level conversion circuit described with reference to FIG.

Second Embodiment Next, a second embodiment of the level conversion circuit according to the present invention will be described with reference to FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the present invention shown in FIG. 2 is a p-channel MIS field-effect transistor in each of the inverters IN ₁ , IN ₂ ... IN _n of the inverter circuit in the level conversion circuit according to the present invention shown in FIG. M1 is replaced by a pnp bipolar transistor for inversion Q '. Therefore, in the level conversion circuit according to the present invention shown in FIG. 1, the "p-channel MIS field-effect transistor" is replaced with a "pnp bipolar transistor for inversion".
"The drain of the p-channel MIS field-effect transistor" is "the collector of the pnp bipolar transistor for inversion", and the "source of the p-channel MIS field-effect transistor" is "emitter of the pnp bipolar transistor for inversion". The "gate of the p-channel MIS field-effect transistor" is replaced with the "base of a pnp bipolar transistor for inversion". The above is the configuration of the second embodiment of the level conversion circuit according to the present invention. According to the level conversion circuit according to the present invention having such a configuration, in the level conversion circuit according to the present invention shown in FIG. ₁ , the inverters IN ₁ and IN _{2 of the} inverter circuit INC are provided.
... Has the same structure as that of the level conversion circuit according to the present invention shown in FIG. 1 except that the p-channel MIS field-effect transistor M1 in IN _n is replaced by a pnp bipolar transistor Q ′ for inversion. Therefore, although detailed description is omitted, excellent operational effects similar to those of the level conversion circuit according to the present invention shown in FIG. 1 can be obtained.

Third Embodiment Next, a third embodiment of the level conversion circuit according to the present invention will be described with reference to FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. The level conversion circuit according to the present invention shown in FIG. 3 is an n-channel MIS field effect transistor M2 in each of the inverters IN ₁ , IN ₂ ... IN _n of the inverter circuit in the level conversion circuit according to the present invention shown in FIG. Is replaced by a first load resistor R '. Therefore, in the level conversion circuit according to the present invention shown in FIG.
"Field effect transistor" is referred to as "first load resistance" and "n
The “drain of the channel-type MIS field-effect transistor” is “one end of the first load resistor”, the “source of the n-channel MIS field-effect transistor” is “the other end of the first load resistor”, and the “p-channel MIS Gate of field-effect transistor and n-channel MIS field-effect transistor "
"The gate of the p-channel MIS field-effect transistor" and "the midpoint of the connection between the drains of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor" The configuration is such that the connection point with the first load resistor or the division point of the second load resistor ”and the“ load resistance ”of the current switching type amplifier circuit are replaced with“ the second load resistor ”. The above is the configuration of the third embodiment of the level conversion circuit according to the present invention. According to the level conversion circuit according to the present invention having such a configuration, in the level conversion circuit according to the present invention shown in FIG. ₁ , the inverters IN ₁ and IN _{2 of the} inverter circuit INC are provided.
... Has the same structure as the level conversion circuit according to the present invention shown in FIG. 1 except that the n-channel MIS field-effect transistor in IN _n is replaced by a first load resistor R ′. Although detailed description is omitted, excellent operational effects similar to those of the level conversion circuit according to the present invention shown in FIG. 1 can be obtained.

Fourth Embodiment Next, a fourth embodiment of the level conversion circuit according to the present invention will be described with reference to FIG. 4, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the present invention shown in FIG. 4 is a p-channel MIS field effect in each of the inverters IN ₁ , IN ₂ ... IN _n of the inverter circuit INC in the level conversion circuit according to the present invention shown in FIG. Transistor M1 is replaced by an inverting pnp bipolar transistor Q 'as in the case of the level conversion circuit according to the present invention shown in FIG. 2, and n-channel MIS field effect transistor M2
Is replaced by the first load resistor RC 'as in the case of the level conversion circuit according to the present invention shown in FIG. 3, and therefore, the "p-channel MIS field effect" in the level conversion circuit according to the present invention shown in FIG. Transistor "to" pnp for invert
Bipolar transistor "and" p-channel MIS "
"Drain of field effect transistor" to "pn for invert
"p-type bipolar transistor collector", "p-channel MIS field-effect transistor source" to "pnp-type bipolar transistor emitter for inversion"
And "gate of p-channel MIS field-effect transistor" as "base of pnp bipolar transistor for inversion", respectively, and "n-channel MI
"S field effect transistor" as "first load resistance"
"Drain of n-channel MIS field-effect transistor" is referred to as "one end of the first load resistor"
The “source of the MIS field-effect transistor” is “the other end of the first load resistor”, and the “gate of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor” is “the gate of the p-channel MIS field-effect transistor”. "And" the connection midpoint of the drains of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor "to" the connection midpoint of the drain of the p-channel MIS field-effect transistor and the first load resistance or 2 load resistor dividing point "and the" load resistor "of the current switching type amplifier circuit are replaced with" second load resistor ". The above is the configuration of the embodiment of the level conversion circuit according to the present invention. According to the level conversion circuit according to the present invention having such a configuration, in the level conversion circuit according to the present invention shown in FIG. ₁ , the inverters IN ₁ and IN _{2 of the} inverter circuit INC are provided.
Except that the p-channel MIS field-effect transistor M1 in IN _n is replaced by a pnp bipolar transistor for inversion and the n-channel MIS field-effect transistor M2 is replaced by a first load resistor R '. Since the configuration is the same as that of the level conversion circuit according to the present invention shown in FIG. 1, detailed description is omitted, but excellent operation and effects similar to those of the level conversion circuit according to the present invention shown in FIG. 1 are obtained. Can be

Embodiments 5 and 6 Next, fifth and sixth embodiments of the level conversion circuit according to the present invention will be described with reference to FIGS. 6 and 7. 6 and 7, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. Level conversion circuit according to the present invention shown in FIGS. 6 and 7, in the level conversion circuit according to the present invention shown in FIGS. 1 and 2, in each of the inverter _{IN 1, IN 2 ......... IN n} , that 1 and 2 except that a diode D is connected in a forward direction with respect to a second power supply terminal E2 in parallel with the n-channel MIS field-effect transistor M2. Having a configuration. The above is the fifth and sixth embodiments of the level conversion circuit according to the present invention.
This is a configuration of an example. According to the level conversion circuit of the present invention having such a configuration, in the level conversion circuit of the present invention shown in FIGS. 1 and 3, the inverter I of the inverter circuit INC is used.
N _1, IN ₂ ......... IN _n in n-channel type MIS field effect transistor M2 and a diode D in parallel are connected, and the inverter IN _i n-channel type MIS field effect transistor M2 connected in parallel with it and diodes However, even if the characteristic drain-source voltage of the n-channel MIS field-effect transistor is going to be high,
Since the drop voltage of the diode D is kept constant, the first
With the level conversion circuit according to the present invention shown in FIG. 2 and FIG. 2, the same operation and effect as described above can be obtained, and the above-described level conversion function can be more stably obtained.

Embodiments 7 and 8 Next, Embodiments 7 and 8 of the level conversion circuit according to the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 and 9, parts corresponding to those in FIGS. 3 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the present invention shown in FIGS. 8 and 9 is different from the level conversion circuit according to the present invention shown in FIGS. 3 and 4 in that the level conversion circuit according to the present invention shown in FIGS. Inverters IN ₁ , INI ₂ ……
In each ... IN _n, in parallel with its first load resistor R ', a diode D is connected. The above is the description of the seventh and eighth embodiments of the level conversion circuit according to the present invention.
This is the configuration of the embodiment. According to the level conversion circuit according to the present invention having such a configuration, in the level conversion circuit according to the present invention shown in FIGS. 3 and 4, the inverter I of the inverter circuit INC is used.
N ₁ , IN ₂ ... A diode D ′ is connected in parallel with the first load resistor R ′ in IN _n, and a diode D connected in parallel with the first load resistor R ′ in the inverter INi. Due to the uneven resistance value of the first load resistor R ', even if the voltage across the first load resistor R' is going to increase, the voltage across the first load resistor R 'can be kept constant at the voltage drop of the diode D. Accordingly, the same level of operation drop as described above can be obtained in the level conversion circuit according to the present invention shown in FIGS. 3 and 4, and the level conversion function described above can be obtained more stably.

Embodiments 9 and 10 Next, ninth and tenth embodiments of the level conversion circuit according to the present invention will be described with reference to FIGS. 10 and 11. FIG. 10 and 11, parts corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. Level conversion circuit according to the present invention shown in FIGS. 10 and FIG. 11, the level conversion circuit according to the present invention shown in FIGS. 1 and 2, in each of the amplifier circuit _{AM 1, AM 2 ......... AM n} , A compensating npn-type bipolar transistor Q ″ is connected in parallel with the load resistance R.
_1, AM ₂ ......... AM _n based compensation npn-type bipolar transistor Q "of having a structure that is connected to the input terminals _{T 1, T 2 ......... T n} . Over the level according to the present invention Ninth and tenth conversion circuits
This is the configuration of the embodiment. According to the level conversion circuit of the present invention having such a configuration, in the level conversion circuit of the present invention shown in FIGS. 1 and 2, the amplification circuit A of the current switching type amplification circuit AMC is used.
M ₁ , AM ₂ ……… For compensation in parallel with the load resistance R at AM _n
except that npn-type bipolar transistor Q "is connected, has a structure similar to that of the level conversion circuit according to the present invention shown in FIGS. 1 and 2, and, the amplifier circuit AM _i
The compensating npn-type bipolar transistor Q ″ connected in parallel with the load resistor R of the above-described type operates in an inverse relationship to the npn-type bipolar transistor requiring amplification, and the compensating npn-type bipolar transistor Q ″ has its input terminal T since the first logic signal a _i from _i is operated by being directly supplied, amplifying npn-type bipolar transistor Q
Operates with a faster rise time as compared with the case where the compensating npn-type bipolar transistor Q ″ is not provided. Therefore, the same operation as described above in the level conversion circuit according to the present invention shown in FIGS. 1 and 2 is achieved. A descent can be obtained and the level conversion function can be obtained faster.

Embodiments 11 and 12 Next, eleventh and twelfth embodiments of the level conversion circuit according to the present invention will be described with reference to FIGS. 12 and 13, parts corresponding to those in FIGS. 3 and 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the invention shown in FIGS. 12 and 13 is different from the level conversion circuit according to the invention shown in FIGS. 3 and 4 in the case of the level conversion circuit according to the invention shown in FIGS. According to, the amplifier circuits AM ₁ and AM ₂ ……… AM
_In each of _n , in parallel with the load resistance R, the compensation npn
Type bipolar transistor Q "is connected, then the amplifier circuit AM _1, AM ₂ ......... AM based Q compensation for the npn bipolar transistor of the _n" input terminal T _1, T ₂ ......... T _n respectively It has a connected configuration. The above is the description of the eleventh and twelfth level conversion circuits according to the present invention.
This is a configuration of an example. According to the level conversion circuit of the present invention having such a configuration, the same operation and effect as those of the level conversion circuit shown in FIGS. 8 and 9 can be obtained, although detailed description is omitted.

Embodiments 13 and 14 Next, 13th and 14th embodiments of the level conversion circuit according to the present invention will be described with reference to FIGS. 14 and 15. 14 and 15, parts corresponding to those in FIGS. 6 and 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the present invention shown in FIGS. 14 and 15 is the same as that of the fifth and sixth embodiments according to the present invention described above with reference to FIGS. As in the case of the ninth and tenth embodiments according to the present invention described above, the structure is the same as that described above with reference to FIGS. 6 and 7, except that a compensating npn-type bipolar transistor is provided. The above is the description of the thirteenth and fourteenth embodiments of the level conversion circuit according to the present invention.
This is the configuration of the embodiment. According to the level conversion circuit according to the second invention of the present application having such a configuration, the fifth and sixth embodiments of the level conversion circuit according to the present invention described above with reference to FIGS. Although the detailed description is omitted because it is the same as that of the embodiment, the same operation and effect as in the fifth and sixth embodiments of the level switching circuit according to the present invention described above with reference to FIGS. The same operation and effect as those of the ninth and tenth embodiments of the level conversion circuit according to the present invention described above with reference to FIG. 11 can be obtained.

Embodiments 15 and 16 Next, fifteenth and sixteenth embodiments of the level conversion circuit according to the first invention of the present application will be described with reference to FIGS. 16 and 17. 16 and 17, parts corresponding to those in FIGS. 8 and 9 are denoted by the same reference numerals, and detailed description thereof will be omitted. The level conversion circuit according to the present invention shown in FIGS. 16 and 17 is the same as that of the seventh and eighth embodiments according to the present invention described above with reference to FIGS. As in the eleventh and twelfth embodiments of the present invention described above, the configuration is the same as that described above with reference to FIGS. 8 and 9 except that a compensating npn-type bipolar transistor is provided. The above is the description of the fifteenth and sixteenth embodiments of the level conversion circuit according to the present invention.
This is the configuration of the embodiment. According to the level conversion circuit according to the second invention of the present application having such a configuration, except for the above-mentioned matter, the seventh and eighth embodiments of the level conversion circuit according to the invention described above with reference to FIGS. Since this embodiment is the same as the embodiment, the detailed explanation is omitted, but the operation and effect similar to those of the embodiment of FIGS. 5 and 6 of the level conversion circuit according to the present invention described above with reference to FIGS. The same operation and effect as the eleventh and twelfth embodiments of the level conversion circuit according to the present invention described above with reference to FIGS. 12 and 13 can be obtained. In the above, only a few embodiments of the present invention have been shown, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief description of the drawings]

FIGS. 1, 2, 3 and 4 are connection diagrams showing first, second, third and fourth embodiments of a level conversion circuit according to the present invention, respectively. Figure 5 is for the logic amplitude V _a of the first logic signal A _i for describing the level conversion circuit according to the present invention shown in FIG. 1,
The relationship between the delay time τ for the first logic signal Ai of the second logic signal B _i, which shows in comparison with the case of the conventional level conversion circuit shown in FIG. 18. FIGS. 6, 7, 8, and 9 are connection diagrams showing fifth, sixth, seventh, and eighth embodiments of the level conversion circuit according to the present invention, respectively. FIGS. 10, 11, 12, and 13 are connection diagrams showing the ninth, tenth, eleventh, and twelfth embodiments of the level conversion circuit according to the present invention, respectively. FIG. 14, FIG. 15, FIG. 16 and FIG. 17 are connection diagrams showing the thirteenth, fourteenth, fifteenth and sixteenth embodiments of the level conversion circuit according to the present invention, respectively. FIG. 18 is a connection diagram showing a conventional level conversion circuit. T ₁ ~T _n ...... input terminals K ₁ ~K _n ...... output terminal INC ...... inverter circuit IN ₁ ~IN _n ...... inverter M1 ...... p-channel type MIS field effect transistor M2 ...... n-channel type MIS field effect transistor D ...... diode AMC ...... current switching換形amplifier AM ₁ ~AM _n ...... amplifier Q ...... amplifying npn-type bipolar transistor R, R '...... load resistor Q' ...... inverted for pnp-type bipolar transistor Q ″… Compensation npn type bipolar transistor H …… Constant current circuit E1, E2, E3 …… Power supply terminal

Claims (8)

(57) [Claims] A plurality of n first logic signals A ₁ , A ₂ each having a level which takes a first logic amplitude although one of them has a logic inversion with respect to all others. ............
A plurality of n input terminals T ₁ to enter the A _n, respectively, T ₂ .........
T _n and a plurality of n-th data having a level that takes a second logic amplitude that is larger than the first logic amplitude, although any one has a logically inverted relationship with respect to all others. in the level conversion circuit having a plurality of n output terminals K _1, K ₂ ......... K _n to output logic signal B ₁ of _2, B 2 ......... B _n, respectively, both p-channel type MIS field effect transistor And a plurality of n inverters IN ₁ and IN ₂ having an n-channel MIS field-effect transistor having a drain connected to the drain of the p-channel MIS field-effect transistor.
... IN _n , and the sources of the p-channel MIS field-effect transistors of the inverters IN ₁ , IN ₂ ... IN _n are connected to a common first power supply terminal, and the inverter IN ₁ , IN ₂ ... IN _n the sources of the n-channel type MIS field-effect transistors are supplied with a voltage lower than the voltage supplied to the common first power supply terminal. Connected to the power supply terminal, the p-channel MIS of the inverters IN ₁ , IN ₂ ……… IN _n
An inverter circuit in which the gates of the field-effect transistor and the n-channel MIS field-effect transistor are commonly connected to the input terminals T ₁ , T _2, ..., T _n , respectively; A plurality of n amplifier circuits AM each having a transistor and a load resistor having one end connected to the collector of the npn-type bipolar transistor for amplification.
1, AM2... AM _n , and the amplifier circuits AM ₁ and AM _2.
The other end of the load resistor of _Mn is connected to the first
Is connected to the power supply terminal, the amplifier circuit AM _1, AM ₂ ......... AM
The emitter of the npn-type bipolar transistor for amplification of _n
The amplifier is connected through a common constant current circuit to a third power supply terminal to which a voltage lower than the voltage supplied to the second power supply terminal is applied with reference to the voltage applied to the first power supply terminal. Circuits AM ₁ , AM ₂ ... AM _n have an npn-type bipolar transistor base for amplification, and the bases of the inverters IN ₁ , IN ₂ ... IN _n are the p-channel MIS field-effect transistors and the n-channel MIS field-effect transistors. The amplifiers AM ₁ , AM _2, ..., AM _n are connected to the collectors of the npn-type bipolar transistors for amplification and the load resistors or the split points of the load resistors, respectively. Is the output terminal K1,
K2... A level conversion circuit having current switching amplifier circuits connected to Kn respectively. 2. A have the relationship but one that is logically inverted with respect to every other, a plurality of n first logic signal A ₁ having a level taking both first logic amplitude, A ₂ ............
A plurality of n input terminals T ₁ to enter the A _n, respectively, T ₂ .........
T _n and a plurality of n-th data having a level that takes a second logic amplitude that is larger than the first logic amplitude, although any one has a logically inverted relationship with respect to all others. in the level conversion circuit having a plurality of n output terminals K _1, K ₂ ......... K _n to output logic signal B ₁ of _2, B 2 ......... B _n, respectively, and both the pnp bipolar transistor for inverting ,
A plurality of inverters IN having an n-channel MIS field-effect transistor having a drain connected to the collector of the pnp bipolar transistor for inversion
1, IN ₂ ……… In _n , and the above inverters IN ₁ , IN ₂ ……
... emitter of the inverted for the pnp bipolar transistor of the IN _n are connected to a common first power supply terminal thereof, the n-channel type MIS field effect transistor of the inverter IN _1, IN ₂ ......... IN _n source, them being connected to the second power supply terminal supplied voltage lower than the reference voltage applied to the common of said first power supply terminal, the inverter iN _1, iN ₂ ......... iN _n the gate of the base and the n-channel type MIS field effect transistor of the inverting for pnp-type bipolar transistor, the common to them, and an inverter circuit connected respectively to the input terminals _{T 1, T 2 ......... T n} , A plurality of n amplifiers each having an amplifying npn bipolar transistor and a load resistor having one end connected to the collector of the amplifying npn bipolar transistor. Circuit A
M ₁ , AM ₂ ... AMn, and the amplifier circuits AM 1, AM _2.
The other ends of the load resistors of AM _n are commonly connected to the first power supply terminal, and the amplifier circuits AM ₁ , AM ₂ ...
The emitter of the npn-type bipolar transistor for amplifying AM _{n has} a voltage lower than the voltage supplied to the second power supply terminal with respect to the voltage supplied to the first power supply terminal through a constant current circuit common to them. The amplifier circuits AM ₁ , AM ₂ ... AM _n are connected to a given third power supply terminal.
Amplifying npn type bipolar base the inverter IN ₁ of the transistor, IN ₂ ......... IN _n each connection point between the drain of the collector and the n-channel type MIS field effect transistor of the inverting for pnp-type bipolar transistor The amplifiers AM ₁ , AM ₂ ... AM _n are connected at the midpoint of connection between the collector of the npn-type bipolar transistor for amplification of AM _n and the load resistor or at the split point of the load resistor.
Level conversion circuit and having a current switching換形amplifier circuit are connected to the output terminal _{K 1, K 2 ......... K n} . 3. A have the relationship but one that is logically inverted with respect to every other, a plurality of n first logic signal A ₁ having a level taking both first logic amplitude, A ₂ ............
A plurality of n input terminals T ₁ to enter the A _n, respectively, T ₂ .........
T _n and a plurality of n-th data having a level that takes a second logic amplitude that is larger than the first logic amplitude, although any one has a logically inverted relationship with respect to all others. in the level conversion circuit having a plurality of n output terminals K _1, K ₂ ......... K _n to output logic signal B ₁ of _2, B 2 ......... B _n, respectively, both p-channel type MIS field effect transistor And a plurality of n inverters IN ₁ , IN ₂ ... IN _n having one end connected to the drain of the p-channel MIS field-effect transistor.
1, IN2 source of the p-channel type MIS field effect transistor of ......... INn are connected to a common first power supply terminal thereof, of the inverter IN _1, IN ₂ ......... IN _n the first The other end of the load resistor is connected to a second power supply terminal to which a voltage lower than the voltage supplied to the first power supply terminal common to them is applied, and the inverters IN ₁ , IN ₂ ,. ... gate of the p-channel type MIS field effect transistor of the iN _n is, the input terminals T _1, T ₂ ......... T _n
, A plurality of n amplifier circuits AM ₁ each having an inverter circuit connected to the amplifier, an amplifying npn-type bipolar transistor, and a second load resistor having one end connected to the collector of the amplifying npn-type bipolar transistor. , AM ₂ ... AM _n , and the amplifier circuits AM ₁ , AM ₂ .
... The other end of the second load resistor of AM _n is commonly connected to the first power supply terminal, and the amplifier circuit A
M ₁ , AM ₂ ... The emitters of the npn-type bipolar transistors for amplification of AM _n are passed through a constant current circuit common to them.
The amplifier circuits AM ₁ and A are connected to a third power supply terminal to which a voltage lower than the voltage applied to the second power supply terminal is applied with reference to the voltage applied to the first power supply terminal.
The base of the npn-type bipolar transistor for amplification of M ₂ ... AM _n is connected between the drain of the p-channel MIS field-effect transistor of the inverter IN ₁ , IN ₂ ... IN _n and the first load resistor. The amplifier circuits AM ₁ , AM ₂ are connected to a middle point or a division point of the first load resistor, respectively.
To ... dividing point of the connection point or the second load resistor between the collector and the second load resistor of the amplifier npn type bipolar transistor of AM _n is, the output terminal K _1, K ₂ ......... K _n And a current switching type amplifier circuit connected to the level conversion circuit. 4. A plurality of n first logic signals A ₁ , A ₂ each having a level that takes a first logic amplitude, although one of them has a logically inverted relationship with respect to all others. ............
A plurality of n input terminals T ₁ to enter the A _n, respectively, T ₂ .........
T _n and a plurality of n-th data having a level that takes a second logic amplitude that is larger than the first logic amplitude, although any one has a logically inverted relationship with respect to all others. in the level conversion circuit having a plurality of n output terminals K _1, K ₂ ......... K _n to output logic signal B ₁ of _2, B 2 ......... B _n, respectively, and both the pnp bipolar transistor for inverting ,
One end of a plurality of n inverter IN _1, IN ₂ ......... IN _n having a first load resistor connected to the collector of the pnp bipolar transistor the inverted, the inverter IN _1, IN ₂ ......... emitter of the inverted for the pnp bipolar transistor of the iN _n are connected to a common first power supply terminal thereof, the inverter IN1, IN2 ......
... The other end of the first load resistor of IN _n is connected to a second power supply terminal to which a lower voltage is applied with reference to a voltage applied to the first power supply terminal common to them. based inverter iN _1, iN ₂ ......... iN _n the inverted for the pnp bipolar transistor of an inverter circuit connected respectively to the input terminals _{T 1, T 2 ......... T n} , both amplifying npn type bipolar transistor and one end having a plurality of n amplifier circuit AM _1, AM ₂ ......... AM _n and a load resistor second being connected to the collector of an npn-type bipolar transistor for the amplification, the amplified Circuits AM ₁ , AM ₂ …
... The other end of the second load resistor of AM _n is commonly connected to the first power supply terminal, and the amplifier circuit A
M ₁ , AM ₂ ... The emitters of the npn-type bipolar transistors for amplification of AM _n are passed through a constant current circuit common to them.
The amplifier circuits AM ₁ and A are connected to a third power supply terminal to which a voltage lower than the voltage applied to the second power supply terminal is applied with reference to the voltage applied to the first power supply terminal.
M ₂ ......... AM base the inverter IN ₁ for amplification npn type bipolar transistor of _n, IN ₂ ......... IN _n in connection with the collector and the first load resistor of the inverting for pnp-type bipolar transistor And the amplifier circuits AM ₁ , AM ₂ ...
...... AM connection point or dividing point of the second load resistor between the collector and the second load resistor of the amplifier npn type bipolar transistor of _n is, the output terminal K _1, K ₂ ......... K _n And a current switching type amplifier circuit respectively connected to the level conversion circuit. 5. The level conversion circuit according to claim ₁ , wherein each of the inverters IN ₁ , IN ₂ ... IN _n is connected in parallel with the n-channel MIS field-effect transistor. , A diode is connected. 6. The level conversion circuit according to claim 3, wherein each of the inverters IN ₁ , IN ₂ ... IN _n is provided with a diode in parallel with the first load resistance. Is connected to the level conversion circuit. 7. The level conversion circuit according to claim ₁ , wherein each of the amplifier circuits AM ₁ , AM ₂ ... AM _n
A compensating npn-type bipolar transistor is connected in parallel with the load resistance, and the base of the compensating npn-type bipolar transistor of the amplifier circuits AM ₁ , AM ₂ ... AM _n is connected to the input terminals T ₁ , T ₂ . ...... Tn
A level conversion circuit, wherein the level conversion circuit is connected to the level conversion circuit. 8. A [Claim 3] or [claim 4] level conversion circuit as claimed in each of the amplifier circuit _{AM 1, AM 2 ......... AM n} ,
A compensating npn-type bipolar transistor is connected in parallel with the second load resistor, and a base of the compensating npn-type bipolar transistor of the amplifier circuits AM ₁ , AM ₂ ... AM _n is connected to the input terminal T ₁ . T ₂ ……… T _n
A level conversion circuit, wherein the level conversion circuit is connected to the level conversion circuit.