JPH042009B2 - - Google Patents
Info
- Publication number
- JPH042009B2 JPH042009B2 JP60085889A JP8588985A JPH042009B2 JP H042009 B2 JPH042009 B2 JP H042009B2 JP 60085889 A JP60085889 A JP 60085889A JP 8588985 A JP8588985 A JP 8588985A JP H042009 B2 JPH042009 B2 JP H042009B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- current source
- constant current
- field effect
- selection control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 76
- 238000001514 detection method Methods 0.000 claims description 34
- 238000006243 chemical reaction Methods 0.000 claims description 27
- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
Landscapes
- Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Description
本発明は、低電位と高電位とをとる小振幅論理
信号を、それが一定の論理振幅をとつていなくて
も検出し、その検出にもとずき、一定の論理振幅
を有する論理信号に変換して出力させる論理信号
検出出力回路に関し、とくに、出力させる論理信
号を、エミツタ結合型バイポーラトランジスタ論
理回路で取扱うようなレベル（低レベルを例えば
−1.6V、高レベルを例えば−0.8Vとするような）
で出力させる論理信号検出出力回路に適用して好
適なものである。
The present invention detects a small amplitude logic signal having a low potential and a high potential even if it does not have a constant logic amplitude, and based on the detection, detects a logic signal having a constant logic amplitude. Regarding the logic signal detection output circuit that converts and outputs the logic signal, it is particularly important to convert the logic signal to a level that is handled by an emitter-coupled bipolar transistor logic circuit (low level is -1.6V, high level is -0.8V, etc.). like that)
The present invention is suitable for application to a logic signal detection output circuit that outputs a logic signal.
従来、第１図を伴つて次に述べる論理信号検出
出力回路が提案されている。
すなわち、能動負荷形の差動振幅回路１と、増
幅回路２と、レベル変換回路３とを有する。
この場合、差動増幅回路１は、（）ソースを
ｐチヤンネル型の負荷用電界効果トランジスタＴ
４でなる負荷回路３１を通じて、高電位電源端子
Ｅ１（例えばOVの電圧が得れる）に接続し、ド
レインを、ｎチヤンネル型の定電流源用電界効果
トランジスタＴ１でなる定電流源回路３３を通じ
て、低電位電源端子Ｅ３（例えば−5.2Vの電圧
が得られる）に接続しているｎチヤンネル型の駆
動用電界効果トランジスタＴ２、（）ソースを、
ｐチヤンネル型の負荷用電界効果トランジスタＴ
５でなる負荷回路３２を通じて、上述した高電位
電源端子Ｅ１に接続し、ドレインを、上述した定
電流源用電界効果トランジスタＴ１でなる定電流
源回路３３を通じて、上述した低電位電源端子Ｅ
３に接続しているｎチヤンネル型の駆動用電界効
果トランジスタＴ３とを有する。
また、増幅回路２は、（）ソースを上述した
高電位電源端子Ｅ１に接続し、ドレインを差動増
幅回路１の出力端としての駆動用電界効果トラン
ジスタＴ３のソースに接続しているｐチヤンネル
型の制御用電界効果トランジスタＴ６と、（）
ｎチヤンネル型の電界効果トランジスタＴ７とｐ
チヤンネル型の電界効果トランジスタＴ８を用い
て構成され、且つ一端を上述した高電位電源端子
Ｅ１に接続し、他端を低電位電源端子Ｅ４（例え
ば−5.2Vの電圧が得られる。ただし、上述した
低電位電源端子Ｅ３でもよい）に接続し、入力端
を差動増幅回路１の駆動用電界効果トランジスタ
Ｔ３のソースに接続しているインバータ３４とを
有する。
さらに、レベル変換回路３は、コレクタを上述
した高電位電源端子Ｅ１に接続し、ベースを上述
した増幅回路２の出力端としてのインバータ３４
の出力端に接続しているレベル変換用バイポーラ
トランジスタＱ１と、そのレベル変換用バイポー
ラトランジスタＱ１と並列に接続されている例え
ば２つのダイオードＤ１及びＤ２の直列回路でな
るダイオード回路３５とを有する。
そして、差動増幅回路１の駆動用電界効果トラ
ンジスタＴ２及びＴ３のゲートから、低電位と高
電位とを互に逆関係にとる小振幅論理信号Vi及び
Ｖiをそれぞれ入力する小振幅論理信号入力端子
IT及びIT′が導出され、また、差動振幅回路１の
負荷回路３１の負荷用電界効果トランジスタＴ４
及び負荷回路３２の負荷用電界効果トランジスタ
Ｔ５のゲートが、駆動用電界効果トランジスタＴ
２のソースに接続され、さらに、定電流源回路３
３の定電流源用電界効果トランジスタＴ１及び増
幅回路２の増幅用電界効果トランジスタＴ６のゲ
ートから、低電位と高電位とをとる選択制御用信
号Vsを入力する選択制御用信号入力端子STが導
出されている。
さらに、レベル変換回路３のレベル変換用バイ
ポーラトランジスタＱ１のエミツタから、低電位
と高電位とをとる論理信号Vpを出力する論理信
号出力端子OTが外部に導出されている。
なお、この論理信号出力端子OTは、外部負荷
抵抗Ｒ（例えば50Ωの抵抗値を有する）を通じて
低電位電源端子Ｅ５（例えば−2Vの電圧が得ら
れる）に接続されているとともに、外部負荷容量
Ｃ（例えば30PFの容量値を有する）を通じて、高
電位電源端子Ｅ２（例えばOVの電圧が得られ
る）に接続されている。
以上が従来提案されている論理信号検出出力回
路の構成である。
このような構成を有する論理信号検出出力回路
によれば、選択制御用信号入力端子STに、選択
制御用信号Vsを高電位で供給すれば、差動増幅
回路１の定電流源回路３３の定電流源用電界効果
トランジスタＴ１が導通状態になり、増幅回路２
の制御用電界効果トランジスタＴ６が非導通状態
になり、論理信号検出出力回路が動作し得る状態
になる。
また、そのような状態から、小振幅論理信号入
力端子IT及びIT′に、小振幅論理信号Vi及びiを
それぞれ供給すれば、それにもとずき、差動増幅
回路１の出力端、従つて駆動用電界効果トランジ
スタＴ３のソースから、小振幅論理信号Vi及び
ｉに比し大きな振幅を有する論理信号が得られ、
また、その大振幅論理信号にもとずき、増幅回路
２から、低電位を低電位電源端子Ｅ４の電圧レベ
ルとし、高電位を高電位電源端子Ｅ１の電圧レベ
ルとする大振幅論理信号が得られ、さらに、その
大振幅論理信号にもとずき、レベル変換回路３の
出力端、従つて、論理信号出力端子OTから、低
電位をダイオード回路３５の両端降下電圧で決ま
る例えば−1.6Vとし、高電位を高電位電源端子
Ｅ１の電圧からレベル変換用バイポーラトランジ
スタＱ１のベース・エミツタ間電圧分降下した例
えば−0.8Vとするようなレベルに変換された論
理信号が、論理信号Vpとして、論理信号出力端
子OTに得られる。
また選択用制御信号入力端子STに、選択制御
用信号Vsを低電位で供給すれば、差動増幅回路
１の定電流源回路３３の定電流源用電界効果トラ
ンジスタＴ１が非導通状態になり、増幅回路２の
制御用電界効果トランジスタＴ６が導通状態にな
り、これにもとずき、増幅回路２のインバータ３
４の電界効果トランジスタＴ８が非導通状態にな
り、論理信号検出出力回路が動作し得ない状態に
なる。
Conventionally, a logic signal detection output circuit has been proposed as described below with reference to FIG. That is, it has an active load type differential amplitude circuit 1, an amplifier circuit 2, and a level conversion circuit 3. In this case, the differential amplifier circuit 1 has the ( ) source connected to a p-channel type load field effect transistor T.
4 is connected to a high potential power supply terminal E1 (for example, OV voltage can be obtained), and the drain is connected to a constant current source circuit 33 consisting of an n-channel constant current source field effect transistor T1. The source of the n-channel driving field effect transistor T2 connected to the low potential power supply terminal E3 (for example, a voltage of -5.2V can be obtained) is
P-channel type load field effect transistor T
5 is connected to the above-mentioned high potential power supply terminal E1, and the drain is connected to the above-mentioned low potential power supply terminal E through the constant current source circuit 33 composed of the above-mentioned constant current source field effect transistor T1.
3, and an n-channel driving field effect transistor T3 connected to the transistor T3. Furthermore, the amplifier circuit 2 is of a p-channel type () whose source is connected to the above-mentioned high potential power supply terminal E1 and whose drain is connected to the source of the driving field effect transistor T3 serving as the output terminal of the differential amplifier circuit 1. control field effect transistor T6, and ()
N-channel field effect transistors T7 and p
It is configured using a channel type field effect transistor T8, and one end is connected to the above-mentioned high potential power supply terminal E1, and the other end is connected to the low potential power supply terminal E4 (for example, a voltage of -5.2V can be obtained.However, the above-mentioned The inverter 34 has an input terminal connected to the source of the driving field effect transistor T3 of the differential amplifier circuit 1. Further, the level conversion circuit 3 has a collector connected to the above-mentioned high potential power supply terminal E1, and a base connected to the inverter 34 as the output terminal of the above-mentioned amplifier circuit 2.
It has a level converting bipolar transistor Q1 connected to the output terminal of the level converting bipolar transistor Q1, and a diode circuit 35 formed of, for example, a series circuit of two diodes D1 and D2 connected in parallel with the level converting bipolar transistor Q1. Then, small amplitude logic signals V i and V i are input from the gates of the driving field effect transistors T2 and T3 of the differential amplifier circuit 1, respectively, with the low potential and high potential having an inverse relationship with each other. input terminal
IT and IT' are derived, and the load field effect transistor T4 of the load circuit 31 of the differential amplitude circuit 1 is derived.
And the gate of the load field effect transistor T5 of the load circuit 32 is connected to the drive field effect transistor T.
2, and further connected to the constant current source circuit 3
A selection control signal input terminal ST is connected to a selection control signal input terminal ST which inputs a selection control signal Vs having a low potential and a high potential from the gates of the constant current source field effect transistor T1 of No. 3 and the amplification field effect transistor T6 of the amplifier circuit 2. It has been derived. Further, from the emitter of the level conversion bipolar transistor Q1 of the level conversion circuit 3, a logic signal output terminal OT is led out to the outside for outputting a logic signal Vp having a low potential and a high potential. Note that this logic signal output terminal OT is connected to a low potential power supply terminal E5 (from which a voltage of -2V is obtained, for example) through an external load resistor R (having a resistance value of, for example, 50Ω), and also connected to an external load capacitor C. (having a capacitance value of, for example, 30 PF) is connected to a high potential power supply terminal E2 (for example, from which a voltage of OV can be obtained). The above is the configuration of the conventionally proposed logic signal detection output circuit. According to the logic signal detection output circuit having such a configuration, when the selection control signal V s is supplied at a high potential to the selection control signal input terminal ST, the constant current source circuit 33 of the differential amplifier circuit 1 is activated. The constant current source field effect transistor T1 becomes conductive, and the amplifier circuit 2
The control field effect transistor T6 becomes non-conductive, and the logic signal detection output circuit becomes operable. In addition, in such a state, if small amplitude logic signals V i and i are supplied to the small amplitude logic signal input terminals IT and IT', respectively, the output terminal of the differential amplifier circuit 1 and the slave From the source of the driving field effect transistor T3, a small amplitude logic signal V i and
A logic signal having a larger amplitude than i is obtained,
Further, based on the large amplitude logic signal, a large amplitude logic signal is obtained from the amplifier circuit 2 that sets the low potential to the voltage level of the low potential power supply terminal E4 and sets the high potential to the voltage level of the high potential power supply terminal E1. Furthermore, based on the large amplitude logic signal, a low potential is set to, for example, -1.6V determined by the voltage drop across the diode circuit 35 from the output terminal of the level conversion circuit 3, and therefore from the logic signal output terminal OT. , a logic signal converted to a level such that the high potential is lowered by the base-emitter voltage of the level-converting bipolar transistor Q1 from the voltage of the high-potential power supply terminal E1 to, for example, -0.8V, is used as the logic signal V p . Obtained at logic signal output terminal OT. Furthermore, if the selection control signal V s is supplied at a low potential to the selection control signal input terminal ST, the constant current source field effect transistor T1 of the constant current source circuit 33 of the differential amplifier circuit 1 becomes non-conductive. , the control field effect transistor T6 of the amplifier circuit 2 becomes conductive, and based on this, the inverter 3 of the amplifier circuit 2 becomes conductive.
The No. 4 field effect transistor T8 becomes non-conductive, and the logic signal detection output circuit becomes inoperable.
第１図に示す従来の論理信号検出出力回路の場
合、小振幅論理信号Vi及びiにもとずき、差動
増幅回路１で大振幅論理信号を得、次でその大振
幅論理信号を増幅回路２で増幅して得られる、そ
の大振幅論理信号を、レベル変換回路３で出力さ
れる論理信号Vpにレベル変換するようにしてい
る。
このため、すなわち、レベル変換をするのに、
差動増幅回路１と増幅回路２とを用いているた
め、論理信号出力端子OTから得られる論理信号
Vpに、小振幅論理信号Vi及びiに対し、無視し
得ない大きな遅延を伴う、という欠点を有してい
た。
よつて、本発明は、上述した欠点のない、新規
な論理信号検出出力回路を提案せんとするもの
で、以下、本発明の実施例を述べるところから明
らかとなるであろう。
実施例 １
第２図は、本発明による論理信号検出出力回路
の第１の実施例を示す。
第２図において、第１図との対応部分には同一
符号を付し、詳細説明を省略する。。
第２図に示す本発明による論理信号検出出力回
路は、次に述べる構成を有する。
すなわち、差動増幅回路４と、レベル変換回路
５とを有する。
この場合、差動増幅回路４は、（）コレクタ
を、第１の負荷用電界効果トランジスタＴ１０と
第１の非線形抵抗６との並列回路でなる第１の負
荷回路８を通じて、高電位電源端子Ｅ１（例えば
OVの電圧が得られる）に接続し、エミツタを、
定電流源回路１０を通じて、低電位電源端子Ｅ３
（例えば、−5.2Vの電圧が得られる）に接続して
いる第１の駆動用バイポーラトランジスタＱ２
と、（）コレクタを、第２の負荷用電界効果ト
ランジスタＴ１１と第２の非線形抵抗６との並列
回路でなる第２の負荷回路９を通じて、上述した
高電位電源端子Ｅ１に接続し、エミツタを、上述
し定電流源回路１０を通じて、上述した低電位電
源端子Ｅ３に接続している第２の駆動用バイポー
ラトランジスタＱ３とを有する。
また、レベル変換回路５は、コレクタを上述し
た高電位電源端子Ｅ１に接続し、ベースを上述し
た差動増幅回路４の出力端としての第２の駆動用
バイポーラトランジスタＱ３のコレクタに接続し
ているレベル変換用バイポーラトランジスタＱ１
を有する。
そして、上述した差動増幅回路４の負荷回路８
の非線形抵抗６、及び負荷回路９の非線形抵抗７
が、それぞれダイオードＤ３、及びＤ４でなる。
また、差動増幅回路４の定電流源回路１０が、
定電流源用バイポーラトランジスタＱ４と定電流
源用電界効果トランジスタＴ９との直列回路でな
る。
さらに、差動増幅回路４の第１及び第２の駆動
用バイポーラトランジスタＱ２及びＱ３のベース
から、低電位と高電位とを互に逆関係にとる第１
及び第２の小振幅論理信号Vi及びiをそれぞれ
入力する第１及び第２の小振幅論理信号入力端子
IT及びIT′が導出されている。
また、差動増幅回路４の第１及び第２の負荷用
電界効果トランジスタＴ１０及びＴ１１のゲート
から、低電位と高電位とをとる第１の選択制御用
信号sを入力する第１の選択制御用信号入力端
子ST′が導出されている。
さらに、定電流源回路１０の定電流源用バイポ
ーラトランジスタＱ４のベースから、定電圧VR
を入力する定電圧入力端子RTが導出されてい
る。
また、定電流源回路１０の定電流源用電界効果
トランジスタＴ９のゲートから、低電位と高電位
とを上述した第１の選択制御用信号sとは逆に
とる第２の選択制御用信号Vsを入力する第２の
選択制御用信号入力端子STが導出されている。
さらに、レベル変換回路５のレベル変換用バイ
ポーラトランジスタＱ１のエミツタから、低電位
と高電位をとる論理信号Vpを出力する論理信号
出力端子OTが導出されている。
また、差動増幅回路４の第２の駆動用バイポー
ラトランジスタＱ３のコレクタが、複数のダイオ
ードＤ５〜Ｄ９の直列回路でなるダイオード回路
１１と制御用電界効果トランジスタＴ１２との直
列回路１２を通じて、低電位電源端子Ｅ４（例え
ば−5.2Vの電圧が得られる。ただし、低電位電
源端子Ｅ３であつてもよい）に接続され、そし
て、制御用電界効果トランジスタＴ１２のゲート
から、低電位と高電位とを上述した選択制御用信
号sと同じにとる第３の選択制御用信号s′が
供給される第３の選択用制御信号入力端子ST″が
導出されている。
以上が、本発明による論理信号検出出力回路の
第１の実施例の構成である。
このような構成を有する本発明による論理信号
検出出力回路によれば、選択制御用信号入力端子
ST、ST′及びST″に選択制御用信号Vs、s、及
びs′をそれぞれ高電位、低電位、及び低電位で
それぞれ供給すれば、差動増幅回路４における定
電流源回路１０の定電流源用電解効果トランジス
タＴ９、負荷回路８の負荷用電界効果トランジス
タＴ１０及び負荷回路９の負荷電界効果トランジ
スタＴ１１がともに導通状態になり、また、直列
回路１２における制御用電界効果トランジスタＴ
１２が非導通状態になり、論理信号検出出力回路
が動作し得る状態になる。
また、このような状態で、小振幅論理信号入力
端子IT及びIT′に小振幅論理信号Vi及びiをそれ
ぞれ供給した場合、小振幅論理信号Vi（または
ｉ）の電位が、定電流源回路１０の定電流源用バ
イポーラトランジスタＱ４のコレクタ電位よりも
駆動用バイポーラトランジスタＱ２（またはＱ
３）のビルトイン電圧（例えば0.8V）だけ高く
なれば、駆動用バイポーラトランジスタＱ２（ま
たはＱ３）が導通状態になり、駆動用バイポーラ
トランジスタＱ３（またはＱ２）が非導通状態に
なる。
このため、駆動用バイポーラトランジスタＱ２
（またはＱ３）のコレクタが、高電位電源端子Ｅ
１の電圧（OV）よりも、負荷回路８における非
線形抵抗６の両端降下電圧（例えば0.8V）分だ
け低い電圧による低い電位になり、一方、駆動用
バイポーラトランジスタＱ３（またはＱ２）のコ
レクタが、高電位電源端子Ｅ１の高い電圧による
高い電位になる。
従つて、駆動用電界効果トランジスタＱ３のコ
レクタ、従つて差動増幅回路４の出力端から、論
理信号（高レベルOV、低レベルを−0.8V）が得
られる。
また、このようにして差動増幅回路４から得ら
れる論理信号が、レベル変換回路５に供給される
ので、そのレベル変換用バイポーラトランジスタ
Ｑ１のエミツタ、従つて、論理信号出力端子OT
に、第１図で上述した従来の論理信号検出出力回
路の場合と同様の、レベル変換された論理信号
Vpが得られる。
また、選択制御用信号入力端子ST、ST′、及
びST″に選択制御用信号Vs、s、及びs′を、
それぞれ低電位、高電位、及び高電位で供給すれ
ば、差動増幅回路４における定電流源回路１０の
定電流源用電界効果トランジスタＴ９、及び負荷
回路８の負荷用電界効果トランジスタＴ１０及び
負荷回路９の負荷用電界効果トランジスタＴ１１
がともに非導通状態になり、直列回路１２の制御
用電界効果トランジスタＴ１２が導通状態にな
る。
このため、高電位電源端子Ｅ１からの電流が、
駆動用バイポーラトランジスタＱ２及びＱ３を通
つて流れなくなり、しかしながら、負荷回路９及
び直列回路１２を通つて流れる。このため、駆動
用バイポーラトランジスタＱ３のコレクタ、従つ
て作動増幅回路４の出力端が、高電位電源端子Ｅ
１の電位から、負荷回路９の非線形抵抗７の両端
降下電圧分だけ下つた電圧による低い電位にな
り、論理信号出力端子OTに、このときの差動増
幅回路４の出力端の低い電位よりもレベル変換用
バイポーラトランジスタＱ１のビルトイン電圧
（例えば0.8V）だけ低い電位を有する出力が得ら
れる。
上述したように、第２図に示す本発明による論
理信号検出出力回路によれば、小振幅論理信号Vi
及びiにもとずき、差動増幅回路４で得られる
大振幅論理信号を、レベル変換回路５で出力され
る論理信号Vpにレベル変換するようにしている。
このため、すなわち、レベル変換をするのに、
第１図で上述した従来の論理信号検出出力回路の
差動増幅回路１に対応している差動増幅回路４の
みを用いているため、論理信号出力端子OTから
得られる論理信号Vpに、小振幅論理信号Vi及び
Ｖiに対し、第１図で上述した従来の論理信号検
出出力回路の場合のような大きな遅延を伴うこと
がない。
また、本発明による論理信号検出出力回路によ
れば、差動増幅回路４を構成している駆動用バイ
ポーラトランジスタＱ２のコレクタと、高電位電
源端子Ｅ１との間に接続されている負荷回路８
が、選択制御用信号sによつて導通及び非導通
状態に選択制御される負荷用電界効果トランジス
タＴ１０と、非線形抵抗６との並列回路でなり、
駆動用バイポーラトランジスタＱ３のコレクタ
と、高電位電源端子Ｅ１との間に接続されている
負荷回路９も、同様に、選択制御用信号sによ
つて導通及び非導通状態に選択制御される負荷用
電界効果トランジスタＴ１１と、非線形抵抗７と
の並列回路でなる。
このため、選択制御用信号Vs、s、及びs′
が低電位、高電位、及び高電位をそれぞれとる非
選択時、駆動用バイポーラトランジスタＱ２及び
Ｑ３には、選択制御用信号Vsによつて定電流源
回路１０の定電流源用電界効果トランジスタＴ９
が非導通状態になることで、電流が流れないが、
負荷回路９及び直列回路１２には、選択制御用信
号sによつて直列回路１２に制御用電界効果ト
ランジスタＴ１２が導通状態になることで、電流
が流れる。しかしながら、このとき、負荷回路９
を構成している負荷用電界効果トランジスタＴ１
１が、選択制御用信号sによつて非導通状態に
なることで、負荷回路９の等価負荷抵抗が非線形
抵抗７による高い値になるので、負荷回路９及び
直列回路１２に流れる電流は少なく、それでい
て、そのような電流が負荷回路９及び直列回路１
２に流れ、そしてこのとき負荷回路９の等価負荷
抵抗が高い値を有しているので、差動増幅回路４
の出力端、従つて、論理信号出力端子OTに、直
列回路１２を有しないことによつて負荷回路９に
電流が流れない場合に比し十分低い電位の出力を
得ることができる。このため、選択制御用信号
Vs、s、及びs′が低電位、高電位、及び高電
位をそれぞれとる非選択時、わずかな消費電力
で、論理信号出力端子OTに十分低い電位の出力
を得ることができる。
また、選択制御用信号Vs、s、及びs′が高
電位、低電位及び低電位をそれぞれとる選択時、
負荷用電界効果トランジスタＴ１０及びＴ１１
が、選択制御用信号Vsによつて導通状態になる
ことで、負荷回路８及び９の等価負荷抵抗がこの
ときの負荷用電界効果トランジスタＴ１０及びＴ
１１による小さい値になるので、駆動用バイポー
ラトランジスタＱ２及びＱ３のコレクタと高電位
電源端子Ｅ１との間の時定数が大きく、従つて、
差動増幅回路４が高速に動作する。
また、差動増幅回路４を構成している駆動用バ
イポーラトランジスタＱ２及びＱ３のエミツタ
と、低電位電源端子Ｅ３との間に接続されている
定電流源回路１０が、定電圧VRによつて制御さ
れる定電流源用バイポーラトランジスタＱ４と、
選択制御用信号Vsによつて導通状態及び非導通
状態に選択制御される定電流源用電界効果トラン
ジスタＴ９との直列回路でなる。
このため、選択制御用信号Vsが低電位をとる
選択時、定電流源用バイポーラトランジスタＱ４
をそれに電流が流れるように制御し、また、選択
制御用信号Vsが高電位をとる非選択時、定電流
源用バイポーラトランジスタＱ４をそれに電流が
流れないように制御するが、その後者の制御が、
定電流源用電界効果トランジスタＴ９を有するこ
とによつて、効果的に行われる。
実施例 ２
図３は、本発明による論理信号検出出力回路の
第２の実施例を示す。
第３図に示す本発明による論理信号検出出力回
路は、差動増幅回路４における定電流源回路１０
が、ベースを定電圧入力端子RTに導出している
定電流源用バイポーラトランジスタＱ４とゲート
を選択用制御信号入力端子STに導出している定
電流源用電界効果トランジスタＴ９との直列回路
でなる第２図に示す本発明による論理信号検出出
力回路の実施例１の場合に代え、ベースを、ゲー
トが選択用制御信号入力端子STに導出されてい
る定電流源用電界効果トランジスタＴ１４を通じ
て定電圧入力端子RTに導出し且つゲートが選択
用制御信号入力端子ST′に導出されている定電流
源用電界効果トランジスタＴ１３を通じて低電位
電源端子Ｅ３に接続している定電流源用バイポー
ラトランジスタＱ４と、定電流源用抵抗１３との
直列回路でなる、第２図に示す本発明による論理
信号検出出力回路の第１の実施例と同様の構成を
有する。
このような構成を有する本発明による論理信号
検出出力回路の第２の実施例によれば、上述した
事項を除いて、第２図に示す本発明による論理信
号検出出力回路の第１の実施例と同様の構成を有
する。
そして、選択用制御信号入力端子ST及び
ST′に選択制御用信号Vs及びsが高電位及び低
電位をそれぞれとつて供給されれば、定電流源用
電界効果トランジスタＴ１４及びＴ１３がそれぞ
れ導通状態及び非導通状態になり、定電流源用バ
イポーラトランジスタＱ４のベースに定電圧入力
端子RTから定電圧が供給される。このため、定
電流源用バイポーラトランジスタＱ４に、第２図
で上述した本発明による、論理信号検出出力回路
の場合と同様に、電流が流れ得る状態になる。
また、選択用制御信号入力端子ST及びST′に
選択制御用信号Vs及びsが低電位及び高電位を
とつて供給されれば、定電流源用電界効果トラン
ジスタＴ１４及びＴ１３がそれぞれ非導通状態及
び導通状態になり、定電流源用バイポーラトラン
ジスタＱ４のベースに低電位電源端子Ｅ３の電位
が与えられる。このため、定電流源用バイポーラ
トランジスタＱ４が、第２図で上述した本発明に
よる論理信号検出出力回路の場合と同様に、非導
通状態になる。
従つて、選択用制御信号入力端子ST及び
ST′に選択制御用信号Vs及びsが高電位及び低
電位をそれぞれとつて供給される選択時において
も、また、選択用制御信号入力端子ST及び
ST′に選択制御用信号Vs及びsが低電位及び高
電位をそれぞれとつて供給される非選択時におい
ても、第２図で上述した本発明による論理信号検
出出力回路の場合と同様の作用効果が得られる。
In the case of the conventional logic signal detection output circuit shown in FIG. 1, based on the small amplitude logic signals V i and i , the differential amplifier circuit 1 obtains a large amplitude logic signal, and then The large-amplitude logic signal obtained by amplification by the amplifier circuit 2 is level-converted into a logic signal V p output by the level conversion circuit 3. For this reason, in order to convert the level,
Since differential amplifier circuit 1 and amplifier circuit 2 are used, the logic signal obtained from the logic signal output terminal OT
V p has a disadvantage in that it is accompanied by a large delay that cannot be ignored with respect to small amplitude logic signals V i and i . Therefore, the present invention aims to propose a novel logic signal detection output circuit free from the above-mentioned drawbacks, which will become clear from the description of embodiments of the present invention below. Embodiment 1 FIG. 2 shows a first embodiment of a logic signal detection output circuit according to the present invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. . The logic signal detection output circuit according to the present invention shown in FIG. 2 has the following configuration. That is, it has a differential amplifier circuit 4 and a level conversion circuit 5. In this case, the differential amplifier circuit 4 connects the ( ) collector to the high potential power supply terminal E1 through the first load circuit 8 formed of a parallel circuit of the first load field effect transistor T10 and the first nonlinear resistor 6. (for example
OV voltage can be obtained) and connect the emitter to
Through the constant current source circuit 10, the low potential power supply terminal E3
(for example, a voltage of -5.2V can be obtained) is connected to the first driving bipolar transistor Q2
The () collector is connected to the above-mentioned high potential power supply terminal E1 through a second load circuit 9 consisting of a parallel circuit of a second load field effect transistor T11 and a second nonlinear resistor 6, and the emitter is connected to the high potential power supply terminal E1. , and a second driving bipolar transistor Q3 connected to the above-mentioned low potential power supply terminal E3 through the above-mentioned constant current source circuit 10. Further, the level conversion circuit 5 has a collector connected to the above-mentioned high potential power supply terminal E1, and a base connected to the collector of the second driving bipolar transistor Q3 serving as the output terminal of the above-mentioned differential amplifier circuit 4. Bipolar transistor Q1 for level conversion
has. Then, the load circuit 8 of the differential amplifier circuit 4 described above
nonlinear resistance 6 of the load circuit 9 and nonlinear resistance 7 of the load circuit 9
are composed of diodes D3 and D4, respectively. Further, the constant current source circuit 10 of the differential amplifier circuit 4 is
It consists of a series circuit of a constant current source bipolar transistor Q4 and a constant current source field effect transistor T9. Further, from the bases of the first and second driving bipolar transistors Q2 and Q3 of the differential amplifier circuit 4, a first
and first and second small amplitude logic signal input terminals into which the second small amplitude logic signals V i and i are respectively input.
IT and IT′ have been derived. Further, a first selection control is performed in which a first selection control signal s having a low potential and a high potential is inputted from the gates of the first and second load field effect transistors T10 and T11 of the differential amplifier circuit 4. A signal input terminal ST' is led out. Further, from the base of the constant current source bipolar transistor Q4 of the constant current source circuit 10, a constant voltage V R
A constant voltage input terminal RT is derived. Further, from the gate of the constant current source field effect transistor T9 of the constant current source circuit 10, a second selection control signal V having a low potential and a high potential opposite to the first selection control signal s described above is generated. A second selection control signal input terminal ST to which s is input is derived. Furthermore, a logic signal output terminal OT is led out from the emitter of the level conversion bipolar transistor Q1 of the level conversion circuit 5, which outputs a logic signal Vp having a low potential and a high potential. Further, the collector of the second driving bipolar transistor Q3 of the differential amplifier circuit 4 is connected to a low potential through a series circuit 12 of a diode circuit 11 consisting of a series circuit of a plurality of diodes D5 to D9 and a control field effect transistor T12. It is connected to the power supply terminal E4 (for example, a voltage of -5.2V can be obtained. However, it may be the low potential power supply terminal E3), and the low potential and high potential are connected from the gate of the control field effect transistor T12. A third selection control signal input terminal ST '' is derived to which a third selection control signal s' , which is the same as the selection control signal s described above, is supplied.The above describes the logic signal detection according to the present invention. This is the configuration of the first embodiment of the output circuit. According to the logic signal detection output circuit according to the present invention having such a configuration, the selection control signal input terminal
By supplying selection control signals V s , s , and s ′ to ST, ST′, and ST″ at high potential, low potential, and low potential, respectively, the constant current source circuit 10 in the differential amplifier circuit 4 can be regulated. The current source field effect transistor T9, the load field effect transistor T10 of the load circuit 8, and the load field effect transistor T11 of the load circuit 9 are all turned on, and the control field effect transistor T in the series circuit 12 is turned on.
12 becomes non-conductive, and the logic signal detection output circuit becomes operable. In addition, in this state, if small amplitude logic signals V i and i are supplied to the small amplitude logic signal input terminals IT and IT', respectively, the small amplitude logic signal V i (or
i ) is lower than the collector potential of the constant current source bipolar transistor Q4 of the constant current source circuit 10, the potential of the driving bipolar transistor Q2 (or Q
If the built-in voltage (for example, 0.8V) of 3) becomes higher, the driving bipolar transistor Q2 (or Q3) becomes conductive, and the driving bipolar transistor Q3 (or Q2) becomes non-conductive. Therefore, the driving bipolar transistor Q2
(or Q3) is connected to the high potential power supply terminal E
1 voltage (OV) by the voltage drop across the nonlinear resistor 6 (for example, 0.8 V) in the load circuit 8, and the collector of the driving bipolar transistor Q3 (or Q2) has a low potential. The potential becomes high due to the high voltage of the high potential power supply terminal E1. Therefore, a logic signal (high level OV, low level -0.8V) is obtained from the collector of the driving field effect transistor Q3, and therefore from the output terminal of the differential amplifier circuit 4. Further, since the logic signal obtained from the differential amplifier circuit 4 in this way is supplied to the level conversion circuit 5, the emitter of the level conversion bipolar transistor Q1, and thus the logic signal output terminal OT
In this case, a level-converted logic signal is generated as in the case of the conventional logic signal detection output circuit described above in FIG.
V p is obtained. In addition, selection control signals V s , s , and s ′ are connected to selection control signal input terminals ST, ST′, and ST ″,
If supplied at low potential, high potential, and high potential, respectively, the constant current source field effect transistor T9 of the constant current source circuit 10 in the differential amplifier circuit 4, and the load field effect transistor T10 of the load circuit 8 and the load circuit. 9 load field effect transistor T11
Both become non-conductive, and the control field effect transistor T12 of the series circuit 12 becomes conductive. Therefore, the current from the high potential power supply terminal E1 is
It no longer flows through the driving bipolar transistors Q2 and Q3, but instead flows through the load circuit 9 and the series circuit 12. Therefore, the collector of the drive bipolar transistor Q3, and hence the output terminal of the differential amplifier circuit 4, is connected to the high potential power supply terminal E.
1, it becomes a lower potential due to the voltage dropped across the nonlinear resistor 7 of the load circuit 9, and the logic signal output terminal OT has a lower potential than the lower potential of the output terminal of the differential amplifier circuit 4 at this time. An output having a potential lower by the built-in voltage (for example, 0.8V) of the level conversion bipolar transistor Q1 is obtained. As described above, according to the logic signal detection output circuit according to the present invention shown in FIG .
Based on and i , the level of the large amplitude logic signal obtained by the differential amplifier circuit 4 is converted into the logic signal V p output by the level conversion circuit 5. For this reason, in order to convert the level,
Since only the differential amplifier circuit 4 corresponding to the differential amplifier circuit 1 of the conventional logic signal detection output circuit described above in FIG. 1 is used, the logic signal V p obtained from the logic signal output terminal OT is For small amplitude logic signals V i and V i , there is no large delay as in the conventional logic signal detection output circuit described above in FIG. Further, according to the logic signal detection output circuit according to the present invention, the load circuit 8 is connected between the collector of the driving bipolar transistor Q2 constituting the differential amplifier circuit 4 and the high potential power supply terminal E1.
is a parallel circuit of a load field effect transistor T10 which is selectively controlled to be in a conductive or non-conductive state by a selection control signal s , and a nonlinear resistor 6,
Similarly, the load circuit 9 connected between the collector of the drive bipolar transistor Q3 and the high potential power supply terminal E1 is also a load circuit whose conduction and non-conduction states are selectively controlled by the selection control signal s . It consists of a parallel circuit of a field effect transistor T11 and a nonlinear resistor 7. Therefore, the selection control signals V s , s , and s ′
When the drive bipolar transistors Q2 and Q3 take low potential, high potential, and high potential, respectively, the constant current source field effect transistor T9 of the constant current source circuit 10 is controlled by the selection control signal Vs.
becomes non-conductive, so no current flows, but
A current flows through the load circuit 9 and the series circuit 12 because the control field effect transistor T12 in the series circuit 12 becomes conductive in response to the selection control signal s . However, at this time, the load circuit 9
The load field effect transistor T1 constituting the
1 becomes non-conductive due to the selection control signal s , the equivalent load resistance of the load circuit 9 becomes a high value due to the nonlinear resistor 7, so the current flowing through the load circuit 9 and the series circuit 12 is small. Nevertheless, such current flows through the load circuit 9 and the series circuit 1.
2, and since the equivalent load resistance of the load circuit 9 has a high value at this time, the differential amplifier circuit 4
By not having the series circuit 12 at the output end of the output terminal, that is, the logic signal output terminal OT, it is possible to obtain an output with a sufficiently lower potential than when no current flows through the load circuit 9. Therefore, the selection control signal
When V s , s , and s ′ are in the non-selected state, each taking a low potential, a high potential, and a high potential, an output of a sufficiently low potential can be obtained at the logic signal output terminal OT with little power consumption. Furthermore, when selecting the selection control signals V s , s , and s ′ to take high potential, low potential, and low potential, respectively,
Load field effect transistors T10 and T11
is turned on by the selection control signal Vs , so that the equivalent load resistance of the load circuits 8 and 9 becomes equal to the load field effect transistors T10 and T at this time.
11, the time constant between the collectors of the driving bipolar transistors Q2 and Q3 and the high potential power supply terminal E1 is large, and therefore,
The differential amplifier circuit 4 operates at high speed. Further, a constant current source circuit 10 connected between the emitters of drive bipolar transistors Q2 and Q3 constituting the differential amplifier circuit 4 and the low potential power supply terminal E3 is powered by a constant voltage VR . a controlled constant current source bipolar transistor Q4;
It consists of a series circuit with a constant current source field effect transistor T9 which is selectively controlled to be in a conductive state or a non-conductive state by a selection control signal Vs. Therefore, when the selection control signal V s is selected to have a low potential, the constant current source bipolar transistor Q4
When the selection control signal V s is at a high potential and is not selected, the constant current source bipolar transistor Q4 is controlled so that current does not flow through it, but the latter control but,
This can be effectively achieved by including the constant current source field effect transistor T9. Embodiment 2 FIG. 3 shows a second embodiment of the logic signal detection output circuit according to the present invention. The logic signal detection output circuit according to the present invention shown in FIG.
is a series circuit consisting of a constant current source bipolar transistor Q4 whose base is led to the constant voltage input terminal RT and a constant current source field effect transistor T9 whose gate is led to the selection control signal input terminal ST. Instead of the case of Embodiment 1 of the logic signal detection output circuit according to the present invention shown in FIG. a constant current source bipolar transistor Q4 connected to the low potential power supply terminal E3 through a constant current source field effect transistor T13 led out to the input terminal RT and whose gate is led out to the selection control signal input terminal ST'; It has the same configuration as the first embodiment of the logic signal detection output circuit according to the present invention shown in FIG. 2, which is composed of a series circuit with the constant current source resistor 13. According to the second embodiment of the logic signal detection output circuit according to the present invention having such a configuration, except for the matters described above, the first embodiment of the logic signal detection output circuit according to the present invention shown in FIG. It has a similar configuration. Then, the selection control signal input terminal ST and
When the selection control signals V s and s are supplied to ST' with high potential and low potential, respectively, the constant current source field effect transistors T14 and T13 become conductive and nonconductive, respectively, and the constant current source A constant voltage is supplied to the base of the bipolar transistor Q4 from the constant voltage input terminal RT. Therefore, a current can flow through the constant current source bipolar transistor Q4 as in the case of the logic signal detection output circuit according to the present invention described above with reference to FIG. Furthermore, when the selection control signals V s and s are supplied to the selection control signal input terminals ST and ST' at low and high potentials, the constant current source field effect transistors T14 and T13 are brought into a non-conducting state, respectively. The transistor becomes conductive, and the potential of the low potential power supply terminal E3 is applied to the base of the constant current source bipolar transistor Q4. Therefore, the constant current source bipolar transistor Q4 becomes non-conductive as in the case of the logic signal detection output circuit according to the present invention described above with reference to FIG. Therefore, the selection control signal input terminals ST and
Also at the time of selection, when the selection control signals V s and s are supplied to ST' with high potential and low potential, respectively, the selection control signal input terminals ST and
Even in the non-selected state where the selection control signals V s and s are supplied to ST′ at low potential and high potential, the same effect as in the case of the logic signal detection output circuit according to the present invention described above in FIG. 2 is obtained. Effects can be obtained.
第１図は、従来の論理信号検出出力回路を示す
接続図である。第２図は、本発明による論理信号
検出出力回路の第１の実施例を示す接続図であ
る。第３図は、本発明による論理信号検出出力回
路の第２の実施例を示す接続図である。
１，４……差動増幅回路、２……増幅回路、
３，５……レベル変換回路、６……非線形抵抗、
８，９……負荷回路、１０……定電流源回路、１
１……ダイオード回路、１２……直列回路、１３
……抵抗、３１，３２……負荷回路、３３……定
電流源回路、３４……インバータ、３５……ダイ
オード回路、Ｄ１〜Ｄ９……ダイオード、Ｅ１，
Ｅ２……高電位電源端子、Ｅ３，Ｅ４，Ｅ５……
低電位電源端子、Ｔ１……定電流源用電界効果ト
ランジスタ、Ｔ２，Ｔ３……駆動用電界効果トラ
ンジスタ、Ｔ４，Ｔ５……負荷用電界効果トラン
ジスタ、Ｔ６……制御用電界効果トランジスタ、
Ｔ７，Ｔ８……電界効果トランジスタ、Ｔ９……
定電流源用電界効果トランジスタ、Ｔ１０，Ｔ１
１……負荷用電界効果トランジスタ、Ｔ１２……
制御用電界効果トランジスタ、Ｔ１３，Ｔ１４…
…定電流源用電界効果トランジスタ、Ｑ１……レ
ベル変換用バイポーラトランジスタ、Ｑ２，Ｑ３
……駆動用バイポーラトランジスタ、Ｑ４……定
電流源用バイポーラトランジスタ。
FIG. 1 is a connection diagram showing a conventional logic signal detection output circuit. FIG. 2 is a connection diagram showing a first embodiment of the logic signal detection output circuit according to the present invention. FIG. 3 is a connection diagram showing a second embodiment of the logic signal detection output circuit according to the present invention. 1, 4... differential amplifier circuit, 2... amplifier circuit,
3, 5...Level conversion circuit, 6...Nonlinear resistance,
8, 9...Load circuit, 10...Constant current source circuit, 1
1...Diode circuit, 12...Series circuit, 13
... Resistor, 31, 32 ... Load circuit, 33 ... Constant current source circuit, 34 ... Inverter, 35 ... Diode circuit, D1 to D9 ... Diode, E1,
E2...High potential power supply terminal, E3, E4, E5...
Low potential power supply terminal, T1... field effect transistor for constant current source, T2, T3... field effect transistor for drive, T4, T5... field effect transistor for load, T6... field effect transistor for control,
T7, T8...field effect transistor, T9...
Field effect transistor for constant current source, T10, T1
1... Load field effect transistor, T12...
Control field effect transistors, T13, T14...
...Field-effect transistor for constant current source, Q1...Bipolar transistor for level conversion, Q2, Q3
... Bipolar transistor for driving, Q4... Bipolar transistor for constant current source.
Claims (1)
の負荷用電界効果トランジスタと第１の非線形抵
抗との並列回路でなる第１の負荷回路を通じて、
高電位電源端子に接続し、エミツタを、定電流源
回路を通じて、低電位電源端子に接続している第
１の駆動用バイポーラトランジスタと、（）コ
レクタを、第２の負荷用電界効果トランジスタと
第２の非線形抵抗との並列回路でなる第２の負荷
回路を通じて、上記高電位電源端子に接続し、エ
ミツタを、上記定電流源回路を通じて、上記低電
位電源端子に接続している第２の駆動用バイポー
ラトランジスタとを有し、 上記レベル変換回路が、コレクタを上記高電位
電源端子に接続し、ベースを上記作動増幅回路の
第２の駆動用バイポーラトランジスタのコレクタ
に接続しているレベル変換用バイポーラトランジ
スタを有し、 上記差動増幅回路の定電流源回路が、定電流源
用バイポーラトランジスタと定電流源用電界効果
トランジスタとの直列回路でなり、 上記差動増幅回路の第２の駆動用バイポーラト
ランジスタのコレクタが、複数のダイオードの直
列回路でなるダイオード回路と制御用電界効果ト
ランジスタとの直列回路を通じて、低電位電源端
子に接続され、 上記差動増幅回路の第１及び第２の駆動用バイ
ポーラトランジスタのベースから、低電位と高電
位とを互に逆関係にとる第１及び第２の小振幅論
理信号をそれぞれ入力する第１及び第２の小振幅
論理信号入力端子が導出され、 上記差動増幅回路の第１及び第２の負荷用電界
効果トランジスタのゲートから、低電位と高電位
とをとる第１の選択制御用信号を入力する第１の
選択制御用信号入力端子が導出され、 上記定電流源回路の定電流源用バイポーラトラ
ンジスタのベースから、定電圧を入力する定電圧
入力端子が導出され、 上記定電流源回路の定電流源用電界効果トラン
ジスタのゲートから、低電位と高電位とを上記第
１の選択制御用信号とは逆にとる第２の選択制御
用信号を入力する第２の選択制御用信号入力端子
が導出され、 上記制御用電界効果トランジスタのゲートか
ら、低電位と高電位とを上記第１の選択制御用信
号と同じにとる第３の選択制御用信号が供給され
る第３の選択制御用信号入力端子が導出され、 上記レベル変換回路のレベル変換用バイポーラ
トランジスタのエミツタから、低電位と高電位を
とる論理信号を出力する論理信号出力端子が導出
されていることを特徴とする論理信号検出出力回
路。 ２ 差動増幅回路と、 レベル変換回路とを有し、 上記差動増幅回路が、（）コレクタを、第１
の負荷用電界効果トランジスタと第１の非線形抵
抗との並列回路でなる第１の負荷回路を通じて、
高電位電源端子に接続し、エミツタを、定電流源
回路を通じて、低電位電源端子に接続している第
１の駆動用バイポーラトランジスタと、（）コ
レクタを、第２の負荷用電界効果トランジスタと
第２の非線形抵抗との並列回路でなる第２の負荷
回路を通じて、上記高電位電源端子に接続し、エ
ミツタを、上記定電流源回路を通じて、上記低電
位電源端子に接続している第２の駆動用バイポー
ラトランジスタとを有し、 上記レベル変換回路が、コレクタを上記高電位
電源端子に接続し、ベースを上記作動増幅回路の
第２の駆動用バイポーラトランジスタのコレクタ
に接続しているレベル変換用バイポーラトランジ
スタを有し、 上記差動増幅回路の定電流源回路が、定電流源
用バイポーラトランジスタと定電流源用抵抗との
直列回路でなり、 上記差動増幅回路の第２の駆動用バイポーラト
ランジスタのコレクタが、複数のダイオードの直
列回路でなるダイオード回路と制御用電界効果ト
ランジスタとの直列回路を通じて、低電位電源端
子に接続され、 上記差動増幅回路の第１及び第２の駆動用バイ
ポーラトランジスタのベースから、低電位と高電
位とを互に逆関係にとる第１及び第２の小振幅論
理信号をそれぞれ入力する第１及び第２の小振幅
論理信号入力端子が導出され、 上記差動増幅回路の第１及び第２の負荷用電界
効果トランジスタのゲートから、低電位と高電位
とをとる第１の選択制御用信号を入力する第１の
選択制御用信号入力端子が導出され、 上記定電流源回路の定電流源用バイポーラトラ
ンジスタのベースから、第１の定電流源用電界効
果トランジスタを通じて、定電圧を入力する定電
圧入力端子が導出され、 上記定電流源回路の定電流源用バイポーラトラ
ンジスタのベースが、ゲートを上記第１の選択制
御用信号入力端子に接続している第２の定電流源
用電界効果トランジスタを通じて、上記低電位電
源端子に接続され 上記定電流源回路の第１の定電流源用電界効果
トランジスタのゲートから、低電位と高電位とを
上記第１の選択制御用信号とは逆にとる第２の選
択制御用信号を入力する第２の選択制御用信号入
力端が導出され、 上記制御用電界効果トランジスタのゲートか
ら、低電位と高電位とを上記第１の選択制御用信
号と同じにとる第３の選択制御用信号が供給され
る第３の選択制御用信号入力端子が導出され、 上記レベル変換回路のレベル変換用バイポーラ
トランジスタのエミツタから、低電位と高電位を
とる論理信号を出力する論理信号出力端子が導出
されていることを特徴とする論理信号検出出力回
路。[Claims] 1. A differential amplification circuit and a level conversion circuit, wherein the differential amplification circuit () has a collector connected to a first
Through a first load circuit consisting of a parallel circuit of a load field effect transistor and a first nonlinear resistor,
A first driving bipolar transistor is connected to a high potential power supply terminal and its emitter is connected to a low potential power supply terminal through a constant current source circuit; a second drive, which is connected to the high potential power supply terminal through a second load circuit configured in parallel with a second nonlinear resistor, and whose emitter is connected to the low potential power supply terminal through the constant current source circuit; and a bipolar transistor for level conversion, wherein the level conversion circuit has a collector connected to the high potential power supply terminal and a base connected to the collector of the second driving bipolar transistor of the differential amplifier circuit. the constant current source circuit of the differential amplifier circuit is a series circuit of a constant current source bipolar transistor and a constant current source field effect transistor; The collector of the transistor is connected to a low potential power supply terminal through a series circuit of a diode circuit consisting of a series circuit of a plurality of diodes and a control field effect transistor, and the collector of the transistor is connected to a low potential power supply terminal through a series circuit of a diode circuit consisting of a series circuit of a plurality of diodes and a control field effect transistor. First and second small-amplitude logic signal input terminals are led out from the base of the transistor, respectively, for inputting first and second small-amplitude logic signals that have a low potential and a high potential in an inverse relationship to each other, and A first selection control signal input terminal for inputting a first selection control signal having a low potential and a high potential is led out from the gates of the first and second load field effect transistors of the dynamic amplifier circuit, A constant voltage input terminal for inputting a constant voltage is derived from the base of the constant current source bipolar transistor of the constant current source circuit, and a low potential and a high voltage input terminal are derived from the gate of the constant current source field effect transistor of the constant current source circuit. A second selection control signal input terminal for inputting a second selection control signal having a potential opposite to that of the first selection control signal is led out from the gate of the control field effect transistor. A third selection control signal input terminal is led out to which a third selection control signal that has the same potential and high potential as the first selection control signal is provided, and is used for level conversion of the level conversion circuit. A logic signal detection output circuit characterized in that a logic signal output terminal for outputting a logic signal having a low potential and a high potential is derived from an emitter of a bipolar transistor. 2 has a differential amplifier circuit and a level conversion circuit, and the differential amplifier circuit has a () collector and a first
Through a first load circuit consisting of a parallel circuit of a load field effect transistor and a first nonlinear resistor,
A first driving bipolar transistor is connected to a high potential power supply terminal and its emitter is connected to a low potential power supply terminal through a constant current source circuit; a second drive, which is connected to the high potential power supply terminal through a second load circuit configured in parallel with a second nonlinear resistor, and whose emitter is connected to the low potential power supply terminal through the constant current source circuit; and a bipolar transistor for level conversion, wherein the level conversion circuit has a collector connected to the high potential power supply terminal and a base connected to the collector of the second driving bipolar transistor of the differential amplifier circuit. the constant current source circuit of the differential amplifier circuit is a series circuit of a constant current source bipolar transistor and a constant current source resistor; The collector is connected to a low potential power supply terminal through a series circuit of a diode circuit including a series circuit of a plurality of diodes and a control field effect transistor, and the collector is connected to a low potential power supply terminal through a series circuit of a diode circuit consisting of a series circuit of a plurality of diodes and a control field effect transistor. First and second small-amplitude logic signal input terminals are led out from the base to input first and second small-amplitude logic signals in which the low potential and the high potential are in an inverse relationship to each other, and the differential amplification described above A first selection control signal input terminal for inputting a first selection control signal having a low potential and a high potential is led out from the gates of the first and second load field effect transistors of the circuit, and A constant voltage input terminal for inputting a constant voltage is led out from the base of the constant current source bipolar transistor of the current source circuit through the first constant current source field effect transistor, and the constant current source bipolar transistor of the constant current source circuit A base of the transistor is connected to the low potential power supply terminal through a second constant current source field effect transistor whose gate is connected to the first selection control signal input terminal. A second selection control signal input that inputs a second selection control signal that takes a low potential and a high potential opposite to the first selection control signal from the gate of the constant current source field effect transistor. a third selection control signal from which a third selection control signal is supplied from the gate of the control field-effect transistor to have the same low potential and high potential as the first selection control signal; and a logic signal output terminal for outputting a logic signal having a low potential and a high potential is derived from the emitter of the bipolar transistor for level conversion of the level conversion circuit. Detection output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60085889A JPS61244120A (en) | 1985-04-23 | 1985-04-23 | Detecting and outputting circuit for logical signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60085889A JPS61244120A (en) | 1985-04-23 | 1985-04-23 | Detecting and outputting circuit for logical signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61244120A JPS61244120A (en) | 1986-10-30 |
| JPH042009B2 true JPH042009B2 (en) | 1992-01-16 |
Family
ID=13871462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60085889A Granted JPS61244120A (en) | 1985-04-23 | 1985-04-23 | Detecting and outputting circuit for logical signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61244120A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2638016B2 (en) * | 1987-12-14 | 1997-08-06 | 株式会社日立製作所 | Semiconductor circuit |
| JP3252903B2 (en) | 1999-05-28 | 2002-02-04 | 日本電気株式会社 | Interface circuit |
| WO2010050543A1 (en) * | 2008-10-30 | 2010-05-06 | ローム株式会社 | Level shifter circuit, load-driving device, and liquid crystal display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664518A (en) * | 1979-10-30 | 1981-06-01 | Nec Corp | Integrated logic circuit |
| JPS5851621A (en) * | 1981-09-22 | 1983-03-26 | Fujitsu Ltd | Electronic circuit |
| JPS60141019A (en) * | 1983-12-28 | 1985-07-26 | Nec Corp | Logic circuit |
-
1985
- 1985-04-23 JP JP60085889A patent/JPS61244120A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5664518A (en) * | 1979-10-30 | 1981-06-01 | Nec Corp | Integrated logic circuit |
| JPS5851621A (en) * | 1981-09-22 | 1983-03-26 | Fujitsu Ltd | Electronic circuit |
| JPS60141019A (en) * | 1983-12-28 | 1985-07-26 | Nec Corp | Logic circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61244120A (en) | 1986-10-30 |
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