JP2003188652A - Gain boost operational amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve driving capability of a gain boost operational amplifier circuit with its circuitry size kept small and without large increase in pausing electrical power consumption. <P>SOLUTION: Such a configuration is adopted that there are provided an input amplifier stage 1, an output stage 2 coupled to an output of the input amplifier stage 1, an input stage bias current source 3 for supplying a bias current to the input amplifier stage 1, and a driving capability amplifier section 4 for varying a control voltage of the input stage bias current source 3 in a direction to increase a bias current thereof according to variation in an output of the input amplifier stage 1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a high speed operational amplifier circuit having a large input dynamic range.

[0002]

2. Description of the Related Art A buffer circuit having an operational amplifier circuit as a voltage follower is often used as a drive circuit having high input impedance and low output impedance.

FIG. 4 is a circuit diagram of a conventional CMOS class AB output operational amplifier circuit (Ron Hogervorst and Johan.
H. Huijsing, "Design of Low-Voltage, Low-Power Ope
rational Amplifier Cells ", Kluwer Academic Publish
ers, pp.154). The operational amplifier circuit of FIG. 4 has an input amplifier stage 4
01 and an output stage 402. Input amplification stage 40
Reference numeral 1 denotes a first folded cascode type operational amplifier circuit having an input differential pair of a first polarity (NMOS configuration) and a second folded cascode type having an input differential pair of a second polarity (PMOS configuration). And an operational amplifier circuit. The first folded cascode operational amplifier circuit includes a first polarity input differential pair 101 connected to an input stage bias current source 102, a first polarity current folding circuit 103, and
It is composed of a first polarity folding bias current source 104 and a second polarity current mirror 105. The second folded cascode type operational amplifier circuit includes an input differential pair 201 of a second polarity connected to an input stage bias current source 202.
A second polarity current folding circuit 203, a second polarity folding bias current source 204, and a first polarity current mirror 205. Then, the first folded cascode type operational amplifier circuit and the second folded cascode type operational amplifier circuit are connected via the first and second couple circuits 301 and 302. MN1
To MN9 are first polarity MOS transistors, MP1 to M
P9 is a second polarity MOS transistor, which is Vin1
And Vin2 are differential input voltages, Vout is an operational amplifier circuit output voltage, Vdd and Vss are power supply voltages, Vbn1 and Vbn2 are bias voltages applied to the first polarity MOS transistors, and Vbp1 and Vbp2 are second polarity MO.
It is a bias voltage applied to the S transistor.

According to the operational amplifier circuit of FIG. 4, the first folded cascode operational amplifier circuit mainly operates when the input signal rises, and the second folded cascode operational amplifier circuit operates when the input signal falls. By working mainly, it operates at high speed at both rising and falling. In addition, folding bias current sources 104 and 204
The drain-source voltage required for the MOS transistor to operate in the saturation region is small, and therefore the input dynamic range is the rail-to-rail voltage, that is, both power supply voltage V
It is almost comparable to the difference between dd and Vss.

[0005]

In order to reduce the power consumption of the operational amplifier circuit of FIG. 4, it is necessary to reduce the aspect ratio of the MOS transistor. However, if the aspect ratio of the MOS transistor is reduced to reduce the power consumption, the transconductance of the output stage 402 is reduced, so that the driving capability of the operational amplifier circuit is reduced.

An object of the present invention is to improve the driving capability of the operational amplifier circuit while keeping the circuit scale small and without increasing the static power consumption so much.

[0007]

To achieve the above object, the present invention provides an input amplification stage, an output stage connected to the output of the input amplification stage, and an input for supplying a bias current to the input amplification stage. A configuration of a gain boost operational amplifier circuit including a stage bias current source and a drive capability amplifying unit for varying the control voltage of the input stage bias current source in the direction in which the bias current increases in accordance with the output variation of the input amplification stage. It was decided to be adopted.

The drive capacity amplifying section according to the present invention detects a change in the output voltage of the input amplifying stage with, for example, a diode-connected MOS transistor (level shifter), and based on the detected change in the output voltage, a newly added couple circuit is used. The control voltage of the input stage bias current source is changed in the direction in which the bias current increases.

The input stage bias current source is operated in the saturation region for M
When an OS transistor is used, the bias current increases in proportion to the square of the voltage fluctuation, so that the amplification efficiency of the driving capability is high. Also, the number of added MOS transistors is small,
The quiescent current required for these is sufficient if they have a value for operating in the saturation region. Therefore, the quiescent current consumption of the entire operational amplifier circuit does not increase significantly. But it is advantageous.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of a gain boost operational amplifier circuit according to the present invention. The operational amplifier circuit of FIG. 1 includes an input amplification stage 1, an output stage 2 connected to the output of the input amplification stage 1, an input stage bias current source 3 for supplying a bias current to the input amplification stage 1, and an input stage. This configuration employs a configuration including a drivability amplifying section 4 for varying the control voltage of the input stage bias current source 3 in the direction in which the bias current increases in accordance with the output variation of the amplification stage 1. Vin1
And Vin2 are differential input voltages, and Vout is an operational amplifier circuit output voltage.

FIG. 2 shows a concrete configuration example of the gain boost operational amplifier circuit according to the present invention. The operational amplifier circuit of FIG. 2 includes a level shifter 501 and a sweep constant current source 5
02, a pull-in constant current source 503, and a third couple circuit 504 are added to the configuration of FIG.

The input stage bias current source 102 for supplying the bias current to the input differential pair 101 of the first polarity is the first
The input-stage bias current source 202 for supplying the bias current to the input differential pair 201 of the second polarity by the MOS transistor MN12 of the polarity is constituted by the MOS transistor MP12 of the second polarity.

The first couple circuit 301 is a first-polarity MOS whose drain and source terminals are connected to each other.
Transistor MN7 and second polarity MOS transistor M
And P7. The second couple circuit 302 is composed of a first-polarity MOS transistor MN8 and a second-polarity MOS transistor MP8 whose drain and source terminals are connected to each other. Third couple circuit 50
Reference numeral 4 denotes a first-polarity MOS transistor MN11 and a second-polarity M1 whose drain and source terminals are connected to each other.
It is composed of an OS transistor MP11 and is connected in parallel with the first couple circuit 301.

The gate terminal of the first-polarity MOS transistor MN12 constituting the input-stage bias current source 102 is connected to the source terminal of the same-polarity MOS transistor MN7 in the first coupling circuit 301, and the input-stage bias current source 20 is connected.
The gate terminals of the second-polarity MOS transistors MP12 constituting the second transistor 2 are connected to the source terminals of the same-polarity MOS transistors MP7 in the first couple circuit 301, respectively.

The source terminal of MN8 in the second couple circuit 302 is a MOS transistor that receives the output of the second folded cascode type operational amplifier circuit (one output of the input amplifier stage 401), that is, the first in the output stage 402. 1
The second terminal is connected to the gate terminal of the polarity MOS transistor MN9.
The source terminal of MP8 in the coupled circuit 302 is a MOS transistor that receives the output of the first folded cascode operational amplifier circuit (the other output of the input amplifier stage 401), that is, the MOS transistor of the second polarity in the output stage 402. Each is connected to the gate terminal of MP9.

The level shifter 501 includes a first polarity MOS transistor MN10 and a second polarity diode-connected MOS transistor MN10, respectively.
It is composed of a polarity MOS transistor MP10. M
The drain terminal and gate terminal of N10 are connected to the sweep-out constant current source 502, and the drain terminal and gate terminal of MP10 are connected to the pull-in constant current source 503, respectively. The source terminal of MN10 is the second couple circuit 302.
The source terminal of MN8 and the gate terminal of MN9 in the output stage 402 are connected to the source terminal of MP8 in the second coupling circuit 302 and the gate terminal of MP9 in the output stage 402, respectively. There is. The gate terminal of MN11 in the third couple circuit 504 is connected to the drain terminal and gate terminal of MN10 in the level shifter 501, and the gate terminal of MP1 in the third couple circuit 504.
The gate terminal of No. 1 is connected to the drain terminal and the gate terminal of MP10 in the level shifter 501, respectively.
As a result, the level shifter 501 level-shifts the outputs of the first and second folded cascode operational amplifier circuits, respectively, and outputs the result of these level shifts to the third level.
Is supplied to the couple circuit 504. In the third couple circuit 504, both MN11 and MP11 are turned off in the balanced state, and either MN11 or MP11 is turned off in the output changing state.
The aspect ratios of MN10, MP10, MN11, and MP11 are adjusted so that the N state is achieved.

In the gain boost operational amplifier circuit of FIG. 2 configured as described above, Vin1 is high and Vin is
When 2 goes low, both outputs of the input amplification stage 401 go low, and MP11 flows a large current in the third couple circuit 504, but MN11 turns off with almost no current flowing and the drain of MP11. The terminal voltage is raised. Therefore, the gate terminal voltage of the MN12 constituting the input stage bias current source 102 is also raised at the same time, and the input stage bias current (drain current of MN12) by the current source 102 increases. At this time, the current flowing through the current mirror 105 also increases,
The drain terminal voltage of MP3 is lowered. Therefore, the gate terminal voltage of MP12 which constitutes the input stage bias current source 202 is also lowered, and the input stage bias current (drain current of MP12) by the current source 202 increases.

On the other hand, Vin1 is low and Vin2 is hi.
When it becomes gh, both outputs of the input amplification stage 401 both become high, and in the third couple circuit 504, MN11 flows a large current, but MP11 hardly flows a current and becomes an OFF state, and the drain terminal voltage of MN11. Is lowered. Therefore, the gate terminal voltage of MP12 which constitutes the input stage bias current source 202 is also lowered at the same time, and the input stage bias current (drain current of MP12) by the current source 202 increases. At this time, the current flowing through the current mirror 205 also increases,
The drain terminal voltage of MN3 is raised. Therefore, the gate terminal voltage of the MN12 constituting the input stage bias current source 102 is also raised, and the input stage bias current (drain current of MN12) by the current source 102 increases.

As described above, according to the gain boost operational amplifier circuit of FIG. 2, the input stage bias current is increased both when the input signal rises and when it falls, so that the driving capability of the operational amplifier circuit is improved.

Moreover, according to FIG. 2, a sweep current source 601 having a current value equal to that of the sweep constant current source 502 is connected to the source terminal of MN11 in the third coupling circuit 504.
The pull-in current source 602 having a current value equal to that of the pull-in constant current source 503 is connected to the MP11 in the third couple circuit 504.
Of the second couple circuit 302 and the current flowing in the first couple circuit 301 by connecting to the source terminals of
The current mirror 205 formed by the first polarity MOS transistors MN3 to MN6.
The deterioration of the mirror precision with the current mirror 105 due to the second polarity MOS transistors MP3 to MP6 is prevented, and the precision of the operational amplifier circuit is improved. However, these current sources 601 and 602 can be omitted.

FIG. 3 shows simulation results of input / output waveforms when the gain boost operational amplifier circuit of the present invention shown in FIG. 2 and the conventional operational amplifier circuit shown in FIG. 4 have voltage follower configurations. In the conventional operational amplifier circuit, the rising and falling edges of the output waveform are slower than the input waveform. On the other hand, the output waveform of the gain boost operational amplifier circuit of the present invention is steep on both the rising and falling sides, and it is understood that the output drive capability is improved.

[0023]

As described above, according to the present invention, an MO transistor which forms an input stage bias current source by adding four MOS transistors and two to four constant current sources.
Reconnecting the gate terminal of the S-transistor brings about a great effect on the improvement of the output drive capability at the time of input fluctuation, without increasing the static current consumption so much.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a gain boost operational amplifier circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of a gain boost operational amplifier circuit according to the present invention.

FIG. 3 is a voltage waveform diagram for explaining the effect of the present invention.

FIG. 4 is a circuit diagram of a conventional operational amplifier circuit.

[Explanation of symbols]

1-input amplification stage 2 output stages 3 input stage bias current source 4 Drive capacity amplifier 101 Input differential pair of the first polarity 102 first-polarity input stage bias current source 103 First-polarity current folding circuit 104 first-polarity current folding bias current source 105 Second polarity current mirror 201 Input differential pair of second polarity 202 second polarity input stage bias current source 203 Second-polarity current folding circuit 204 Bias current source for current folding of second polarity 205 First-polarity current mirror 301 First Couple Circuit 302 Second Couple Circuit 401 Input amplification stage 402 output stage 501 level shifter 502 Swept out constant current source 503 Pull-in constant current source 504 Third Couple Circuit 601 Sweep current source 602 Current source MN1 to MN12 first polarity MOS transistor MP1 to MP12 second polarity MOS transistor Vbn1, Vbn2 bias voltage Vbp1, Vbp2 bias voltage Vdd, Vss power supply voltage Vin1, Vin2 differential input voltage Vout Operational amplifier circuit output voltage

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hirofumi Nakagawa             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Jun Iizuka             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Hiroshi Kojima             1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Sith             Tem Techno Co., Ltd. (72) Inventor Tomokazu Kojima             1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Sith             Tem Techno Co., Ltd. F term (reference) 5J092 AA01 AA13 AA47 CA32 CA35                       CA81 FA10 HA10 HA17 KA05                       KA09 KA12 MA17 MA22 TA01                       TA06 VL06                 5J100 JA01                 5J500 AA01 AA13 AA47 AC32 AC35                       AC81 AF10 AH10 AH17 AK05                       AK09 AK12 AM17 AM22 AT01                       AT06 LV06

Claims (4)

[Claims] 1. An input amplification stage, an output stage connected to an output of the input amplification stage, an input stage bias current source for supplying a bias current to the input amplification stage, and an output fluctuation of the input amplification stage. In accordance with the above, a gain boost operational amplifier circuit is provided, which further comprises a drive capability amplifier section for varying the control voltage of the input stage bias current source in the direction in which the bias current increases. 2. An input amplification stage, an output stage connected to an output of the input amplification stage, an input stage bias current source for supplying a bias current to the input amplification stage, and an output fluctuation of the input amplification stage. And a drive capability amplifying unit for varying the control voltage of the input stage bias current source in the direction in which the bias current increases.
Type gain boost operational amplifier circuit, wherein the input amplifier stage includes a first differential input differential pair having a first polarity.
Of the folded cascode operational amplifier circuit and a second folded cascode operational amplifier circuit having an input differential pair of the second polarity are connected via the first and second couple circuits. The input-stage bias current source supplies a bias current to the first-polarity input differential pair and a first-polarity MOS transistor for supplying a bias current to the first-polarity input differential pair. Each of the first and second couple circuits has a first polarity and a second polarity, the drain and source terminals of which are connected to each other.
A gate terminal of each MOS transistor which has a polarity MOS transistor and constitutes the input stage bias current source is connected to a source terminal of the same polarity MOS transistor in the first coupling circuit, The source terminal of each MOS transistor in the couple circuit is connected to each of the two outputs of the input amplification stage, and the drive capability amplification unit is configured such that the drain terminal / source of the first couple circuit according to the output variation of the input amplification stage. Gain boost operational amplification, characterized in that the voltage at the gate terminal of each MOS transistor of the input stage bias current source is changed in the direction in which the bias current increases by decreasing the voltage between the terminals. circuit. 3. The gain boost operational amplifier circuit according to claim 2, wherein the drive capability amplifier is connected in parallel with the level shifter connected to two outputs of the input amplifier stage and the first couple circuit. And a third couple circuit, wherein the level shifter has diode-connected first polarity and second polarity MOS transistors, and the diode-connected first polarity MOS transistor has a drain terminal for sweeping out a constant current. The source terminal of the diode-connected first polarity MOS transistor is the source terminal of the first polarity MOS transistor in the second couple circuit, and the source terminal of the diode-connected second polarity MOS transistor is The terminal is a pull-in constant current source, and the diode-connected second polarity MO
The source terminals of the S transistors are respectively connected to the source terminals of the second polarity MOS transistors in the second couple circuit, and the third couple circuit is the first drain terminal and the source terminal of which are connected to each other. A gate terminal of the first polarity MOS transistor in the third coupling circuit, and a gate terminal of the diode-connected first polarity MOS transistor, A gain boost operational amplifier circuit, characterized in that the gate terminals of the second polarity MOS transistors in the couple circuit are respectively connected to the gate terminals of the diode-connected second polarity MOS transistors. 4. The gain boost operational amplifier circuit according to claim 3, wherein a sweep current for flowing the same current as the sweep constant current source to the source terminal of the MOS transistor of the first polarity in the third couple circuit. And a pull-in current source for supplying the same current as the pull-in constant current source to the source terminal of the second polarity MOS transistor in the third couple circuit. Amplifier circuit.