JPS59154069A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacitance between the first and second gate electrodes and thus reduce the write voltage into the second gate electrode by a method wherein the first gate electrode is so provided as to cross a part of an island region of a substrate, and the second gate electrode is so provided that a part thereof bites into the side surface of the first gate electrode. CONSTITUTION:A PROM memory cell has a structure having the first gate electrode 24 crossing a part on the element region 13 via the first gate oxide film 23 and having constrictions 19a and 19b, which direct inward, on side surfaces at both ends and the second gate electrode 26 which is laminated on said electrode 24 via the second gate oxide film 25 and has the form that a part bites into the constrictions 19a and 19b of said electrode 24 via said film 25. Thereby, since the surface area of the first gate electrode 24 to the second gate electrode 26 can be increased, the capacitance between the first and second gate electrodes 24 and 26 can be remarkably increased. Therefore, the write voltage into the second gate electrode 26 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a non-volatile semiconductor memory device and a method for manufacturing the same.

[Technical background of the invention]

Non-volatile semiconductor memory devices, such as FROM (Progr.
2. Description of the Related Art As an available read only memory, one having a memory cell structure shown in FIGS. 1 and 2 is conventionally known. That is, 1 in the figure is a p-type semiconductor substrate, and this substrate 1 is provided with a field oxide film (element isolation region) 3 for isolating element regions 2. As shown in FIG. This element region 2 is provided with n+ type source and drain regions 4 and 5 which are electrically isolated from each other. A first dirt electrode (floating dirt electrode) 7 made of, for example, impurity-doped polycrystalline silicon is provided on a portion of the device region 2 including the channel region between these source and drain regions 4 and 5 via a first gate insulating film 6. It is being Further, a second dirt electrode (control gate electrode) 9 made of, for example, impurity doped polycrystalline silicon is laminated on the first dirt electrode 7 with a second dirt insulating film 8 interposed therebetween. Note that both ends of the first dirt electrode 7 extend in the channel width direction, and parts of these ends overlap on the field oxide film 3. Further, an insulating film 10 is formed on the exposed side surface of the first dirt electrode 7 and around the second dirt electrode 9. In such a FROM, hot carriers generated in the channel region by applying a high voltage to the second dirt electrode 9 and the n-type drain region 5 are transferred to the first dirt electrode 7 through the first dirt insulating film 6.
The memory function is maintained in a predetermined memory cell by injecting and accumulating the voltage and changing the threshold voltage (Vth).

By the way, when the FROM shown in FIGS. 1 and 2 mentioned above schematically shows the electrical circuit at the time of writing, the voltage vFo of the floating gate electrode 7 and the control gate are as shown in FIG. Voltage V of the top electrode 9. There is a relationship between G as shown in the following formula.

Here, C1 is the capacitance between the substrate 1 and the 70-channel electrode 7, C2 is the capacitance between the floating gate electrode 7 and the control gate electrode 9, and c, 3 is the capacitance between the drain region 5 and the 70-channel electrode 7. The capacitance of the overlapped portion with the pole 7 is shown, and VD is the drain voltage.

Writing into the FROM is determined by the voltage vFo of the floating gate electrode 7, and what actually controls vFG is the voltage of the control ff-) electrode 9. . It is. That is, vF
The proportionality coefficient between o and Vco is C2/c, and in order to be able to write at a low voltage, it is simply necessary to increase the capacitance C2 between the electrode 7 and the control gate electrode 9.

[Problems with background technology]

However, in the prior art, the so-called write voltage applied to the control dart electrode even in the case of 64 EFROM devices requires a high voltage of 21V. In particular, as devices become smaller in the future, lower write voltages will be required. Therefore, one possible method for increasing the capacitance C2 between the dirt electrodes is to make the second dirt insulating film 8 shown in FIG. That is difficult.

[Purpose of the invention]

The present invention aims to provide a semiconductor memory device and a method for manufacturing the same, which can increase the capacitance between the first and second dart electrodes without causing deterioration of device characteristics, and further reduce the write voltage. .

[Summary of the invention]

In the present invention, a first dirt electrode is provided so as to at least traverse a part of an island-like region of a semiconductor substrate via a first dirt insulating film, and a second dirt electrode is provided on a region including the dirt electrode so that a part of the island-like region of the semiconductor substrate is traversed. By providing the second dirt insulating film so as to bite into at least the side surface of the first dirt electrode, the capacitance between the first and second dirt electrodes is increased, and the second dirt electrode
The main idea is to reduce the write voltage to the dirt electrode.

That is, the first invention of the present application provides a semiconductor memory device including two or more layers of gate electrodes in island-like regions of a semiconductor substrate separated by an element isolation region, in which a first dirt electrode is connected to one of the island-like regions. A second dirt electrode is provided at least across the first dirt oxide film, and a second dirt electrode is provided on the region including the dirt electrode.
The present invention is characterized in that the dirt electrodes are laminated with a second dirt insulating film interposed therebetween so that a part of the dirt electrodes bites into at least the side surface of the first dirt electrode.

As the material for the gate electrode, for example, impurity-doped polycrystalline silicon, impurity-doped amorphous silicon, or high melting point metal silicide such as molybdenum silicide, tungsten silicide, tantalum silicide, platinum silylide, etc. can be used.

The shape of the first dart electrode is, for example, such that an elongated inwardly constricted portion is formed on the side surface of at least one end. In addition, this constriction is not limited to one, but the first
A plurality of electrodes may be provided on the side surface of the dart electrode in the thickness direction thereof. A second dirt electrode is attached to the first dirt electrode.
By stacking the dirt insulating film therebetween, a part of the second dirt electrode enters the constriction of the first dirt electrode,
Effective first. The capacitance between the second dart electrodes is dramatically improved.

Further, the second invention of the present application provides a method for manufacturing a semiconductor memory device having two or more layers of r-) electrodes on an island region of a semiconductor substrate separated by an element isolation region.
A step of depositing a first layer electrode material film to become a first dirt electrode on the entire surface including the insulating film, a step of forming a film pattern made of a sublimable material on the first layer electrode material film, and a step of depositing a first layer electrode material film on the entire surface including the insulating film. 1 After depositing the second layer electrode material film that will become the dart electrode,
selectively forming an I mask material on the electrode material film 4', selectively etching the second layer electrode material film using this mask material, and exposing a part of the film pattern; , forming a second layer electrode material pattern whose end portions overlap the coating pattern; and after sublimating and removing the coating pattern, selectively removing the first layer electrode material film using the mask material; forming an electrode material no-turn having an inwardly elongated constriction on the side surface of the end from the first layer electrode material pattern and the second layer electrode material pattern by etching; a step of forming a second insulating film around the electrode material/gut; a step of depositing a second dirt electrode material film over the entire surface and sufficiently wrapping a portion of the second dirt electrode material film around the constriction of the electrode material/gut; A first dirt electrode having a constricted portion on the end side surface is formed by sequentially selectively etching the second dirt electrode material film to the electrode material cutter, and a second dirt insulating film is formed on the first dirt electrode. The method is characterized by comprising a step of forming a second gate electrode having a shape in which the dirt electrodes are laminated and a part of the dirt electrodes is dug into the constriction part of the dart electrode through the second gate insulating film. be.

The nine turns of the coating made of the sublimable material are used to form a constricted portion on the side surface of the electrode material pattern that will become the first gate electrode by subliming and removing the /e turns. Examples of such sublimable materials include MO and W.

The mask material is desirably made of a heat-resistant material because it needs to remain even when the coating A is removed by sublimation. Such heat-resistant materials include, for example, SiO, 5t6
N4. At206 etc. can be mentioned.

In addition, by forming the electrode material pattern that will become the first dart electrode with three or more layers of electrode material films, and interposing a film pattern between each of these electrode material films, a constricted portion is formed on the side surface of the end portion. The first one made in two or more directions
A dart electrode can be formed.

[Embodiments of the invention]

Next, a manufacturing process for illustrating a FROM memory cell, which is an embodiment of the present invention, will be described in detail.

(1) First, after forming a field oxide film (device isolation region) 12 on a p-type silicon substrate 11 by selective oxidation or the like, for example, an island region (device region) 13 of the substrate 11 separated by the field oxide film 12 is formed. A first thermal oxide film 14 having a thickness of 500×, which becomes a first dirt oxide film, was formed on the surface by thermal fermentation.

Next, a second layer phosphorus-doped polycrystalline silicon film 15 with a thickness of 2000X, for example, is deposited on the entire surface by CVD, and a Mo film with a thickness of 3000X is further deposited, and this is patterned to form a periphery including the element region 13. MO/'e turns 16 were formed which were opened in a strip shape in the channel length direction (as shown in FIG. 4(a)).

(11) Next, after depositing a second layer phosphorus-doped polycrystalline silicon film (not shown) with a thickness of 2000X on the entire surface, and further depositing a SiO□ film with a thickness of 2000X on the entire surface,
An S10□ pattern (mask material) 17 was formed by etching the iO2 film using photoetching technology. Subsequently, using the 5i02 pattern 17 as a mask, the second layer phosphorus-doped polycrystalline silicon film is selectively removed by, for example, RIE to expose a part of the Mo pattern 16 and to ensure that both ends overlap the Mo pattern 16. A first layer polycrystalline silicon pattern 20 having a defined length in the channel width direction was formed (as shown in FIG. 4(b)).

011) Next, thermal oxidation treatment was performed in an oxygen atmosphere at 900°C. At this time, as shown in FIG. 4(c), the Mo pattern 16 is oxidized and sublimated as molybdenum oxide,
Constricted portions 19g and 19 are formed below the portion of the second layer polycrystalline silicon pattern 18 that overlaps with the MO turn 16.
b was formed.

Next, RIE using 5102 pattern 17 as a mask.
After selectively removing the first layer polycrystalline silicon film 15 to form a first layer polycrystalline silicon pattern 20, the S+02 pattern 17 was removed (FIG. 4(d)).
and Figure 5). Note that FIG. 5 is a plan view of FIG. 4(d). As a result of this patterning, the first layer polycrystalline silicon patterns 200, . 1 B
A polycrystalline silicon turf 21 was formed.

Subsequently, a second thermal oxide film 22 was formed around the polycrystalline silicon pattern 21 by thermal oxidation treatment (see FIG. 4).
,) as shown).

Ov) Next, a lindozopolycrystalline silicon film having a thickness of, for example, 4000× is deposited on the entire surface, and the constriction portion 19a of the polycrystalline silicone 4-turn 21 is formed.

The polycrystalline silicon was fully inserted up to 195 mm.

Subsequently, a resist pattern (not shown) is formed by photolithography on the second dust electrode formation portion of this polycrystalline silicon film, and then, using this resist/4' turn as a mask, phosphorus dope is applied to form the second dust electrode. The polycrystalline silicon film, the second thermal oxide film, the polycrystalline silicon A turn serving as the first dirt electrode, and the first thermal oxide film were selectively removed by, for example, RIE. With this, the first r-) from the board 11 side
Oxide film 23 has constricted portions 19a at both ends.

A first dirt electrode (floating dirt electrode) 24 having a diameter of 19b is laminated on the first dirt electrode 24 with a second dirt oxide film 25 interposed therebetween, and a part of the dirt electrode 24 is
Second dart electrodes (control gate electrodes) 26 were formed in the constricted portions 19a and 19b of the substrate through the second dirt oxide film 25, respectively. Subsequently, after removing the resist pattern, ions of an n-type impurity, such as arsenic, are implanted into the element region 13 of the substrate 11 using the second date electrode 26 and the left mask of the field oxide film 12, and heat treatment is performed to activate and diffuse the impurity. Then, n-type source and drain 1N regions 2.7 and 28 were formed, and a FROM memory cell was manufactured (as shown in FIGS. 4(f) and 6). Note that FIG. 6 is a plan view of FIG. 4(f).

Therefore, the memory cell of the FROM of the present invention is shown in FIG.
) and as shown in FIG.
The first f- crosses through the dirt oxide film 23 and has inwardly constricted portions 19a + 19b on the side surfaces at both ends.
A dirt electrode 24 is laminated on the first dirt electrode 24 with a second dirt oxide film 25 interposed therebetween, and a portion is formed on the constricted portions 19m and 19b of the r-) electrode 24 via the same oxide film 25. It has a structure including a second dirt electrode 26 having a deep shape. Therefore, since the surface area of the first dirt electrode 240 relative to the second gate electrode 26 can be increased, the surface area of the first dirt electrode 240 relative to the second gate electrode 26 can be increased.
The capacitance between the second dart electrodes 24 and 26 can be dramatically increased. Therefore, the write voltage to the second dart electrode (control dart electrode) 26 can be reduced, and the voltage can be lowered as a result of miniaturization of memory cells.

Moreover, when the capacitance is the same as that of the conventional structure, the area of the first dart electrode (floating dart electrode) 24 can be reduced, and the element (memory cell) can be miniaturized.

Further, according to the present invention, the first. 2nd dart electrode 24.26
Since there is no need to reduce the thickness of the second dirt oxide film 25 in between, a decrease in breakdown voltage can be avoided.
The constricted portion 19a, which is involved in increasing the surface area of the first gas electrode 24 by removing the O/lean 16 by sublimation,
19b, the first. A FROM memory cell with increased capacitance between the second dirt electrodes 24 and 26 can be easily manufactured. Moreover, said No/'? p-
Since the sublimation step of the tube 16 can be carried out in an oxidizing atmosphere at a temperature of 70° C. or higher, it can be sufficiently applied to future low-temperature processes.

Furthermore, according to the method of the present invention, the thickness of the No pattern 16 can be adjusted, and the constriction 19a is formed by sublimation and removal of the Mo pattern 16.

The thickness of the electrode 19b can be changed arbitrarily, and thus the capacitance between the first and second dart electrodes 24, 25 can be easily controlled.

In the above embodiment, the sublimation and removal of the MO pattern and the thermal oxidation of the polycrystalline silicon pattern were performed in separate steps, but they may be performed in the same step.

In the above example, MO/'? Turn first. The first layer has one constriction on each end side surface by interposing the second layer of phosphorous-doped polycrystalline silicon and the turns.
) electrodes were formed; however, the present invention is not limited thereto. For example, three or more layers (specifically, three layers) of phosphorus-doped polycrystalline silicon films are used, and each N
By interposing an oI or a turn (two layers), the first dirt electrode 24 has two constrictions 19m, 19s: + 19b, and 19W in the thickness direction on the side surfaces of both ends, respectively, as shown in the seventh image. may be formed, and a second dirt electrode 26 may be laminated on this electrode 24 with a second dirt oxide film 25 interposed therebetween. According to such a configuration, the surface area of the first dirt electrode 240 relative to the second dirt electrode 26 is further increased, so that the write voltage to the second dirt electrode 26 can be further reduced.

Further, the present invention is not limited to the FROM memory cell as in the above embodiment, but can be similarly applied to a dynamic RAM memory cell. With such a dynamic RAM, it is possible to improve device characteristics by increasing storage capacity, and to dramatically improve device integration and miniaturization.

〔Effect of the invention〕

As described in detail above, according to the present invention, the first. It is possible to provide a semiconductor memory device in which the capacitance between the second dart electrodes can be increased and a write voltage can be reduced, as well as a method for easily manufacturing such a semiconductor memory device.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a conventional FROM memory cell, Fig. 2 is a cross-sectional view of the two-layer dirt electrode section of the memory cell of Fig. 1 cut in the channel length direction, and Fig. 3 is a cross-sectional view of a FROM memory cell. Schematic diagrams schematically showing electrical circuits during writing, FIGS. 4(a) to 4(f) are
5 is a plan view of FIG. 4(d), FIG. 6 is a plan view of FIG. 4(f), and FIG. 7 is a plan view of another embodiment of the present invention. FIG. 2 is a cross-sectional view of an exemplary FROM memory cell. 11...2m silicon substrate, 12...field oxide film (element isolation region), 13...element region, 15...
・First layer lindozo polycrystalline silicon film, 16...MO
Noya turn, 17...S 102 patterns, 18...
・Second layer polycrystalline silicon pattern, 19m+19br1
9a', 19b'... Narrow portion, 20... Second layer polycrystalline silicon pattern, 21... Polycrystalline silicon pattern, 23... First dirt oxide film, 24... First dirt electrode (Floaty〉'Gugut electrode), 25...
Second gate oxide film, 26... Second dirt electrode (control gate electrode), 27... nn source region, 2
8...n-type drain region. Applicant's agent Patent attorney Takehiko Suzue Figure 5 Figure 6

Claims (8)

[Claims] (1) In a semiconductor memory device having two or more layers of dirt electrodes on an island region of a semiconductor substrate separated by an element isolation region, a first dirt electrode is formed by forming a part of the island region with a first dirt oxide film. and a second dirt electrode is laminated on the region including the dirt electrode with a second gate insulating film interposed therebetween so that a part of the second dirt electrode digs into at least the side surface of the first gate electrode. A semiconductor memory device characterized by: (2) At least one end side surface of the first dirt electrode has an inwardly constricted shape, and a part of the second date electrode is laminated on the first dirt electrode with a second dirt insulating film interposed therebetween. 2. The semiconductor memory device according to claim 1, wherein the first dirt electrode is inserted into the constricted portion of the first dart electrode. (3) The semiconductor memory device according to claim 1, wherein a plurality of elongated constrictions are provided on at least one end side surface of the first dart electrode in the thickness direction of the dart electrode. (4) In manufacturing a semiconductor memory device having two or more layers of gate electrodes on an island region of a semiconductor substrate separated by an element isolation region, a first dirt layer is formed on the entire surface including the first insulating film on the island region. A step of depositing a first layer electrode material film that will become an electrode, a step of forming four turns of a film made of a sublimable material on this first layer electrode material film, and a step of depositing a second layer electrode material film that will become a first dirt electrode on the entire surface. After depositing the layer electrode material film, a step of selectively forming an IQ mask material on the electrode material film and selectively etching the second layer electrode material film using this mask material to form a part of the film pattern. forming a second layer electrode material pattern whose end portions overlap the coating pattern; and after removing the coating pattern by sublimation, using the mask material to A step of forming an electrode material pattern having an inwardly elongated constriction on the end side surface of the first layer electrode material pattern and the M2 layer electrode material pattern by selectively etching the electrode material film. a step of forming a second insulating film around the electrode material/cutane; a step of depositing a second dirt electrode material film over the entire surface and sufficiently wrapping a portion of the second dirt electrode material film around the constriction of the electrode material pattern; at least the second
The first electrode material film having a constricted portion on the side surface of the end portion is selectively etched sequentially from the r-toe electrode material film to the electrode material pattern.
a date electrode, and a second electrode layer laminated on the 14''-) electrode with a second dirt insulating film interposed therebetween, and a second part having a shape that partially bites into the constriction of the dart electrode through the second dirt insulating film.
1. A method of manufacturing a semiconductor memory device, comprising the step of forming a dirt electrode. (5) The method for manufacturing a semiconductor memory device according to claim 4, wherein the sublimable material is MO or W. (6) The method of manufacturing a semiconductor memory device according to claim 4, wherein the mask material is made of a heat-resistant material. (7) The method for manufacturing a semiconductor memory device according to claim 6, wherein the heat-resistant material is SiO2 or Si3N4. (8) The electrode material and pattern for the first gate electrode are 3
The coating A is formed from more than one layer of electrode material films, and is made of a sublimable material between the electrode material films. 8. The method of manufacturing a semiconductor memory device according to claim 4, wherein a turn is interposed between each of the semiconductor memory devices.