JPH01128472A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To assure high integration without reducing the capacitance coupling ratio in a memory transistor region by extending a second gate of the memory transistor region to the upper of a gate of another transistor region. CONSTITUTION:A cell in a region L1 is formed of two transistor regions 1, 2 of storage and selection. A first gate 13 of a selection transistor region 2 is formed of a polysilicon film, and part of a first insulating film 8 serves as a tunnel insulating film 7, the former film being formed in contact with the lower part of a second gate 6 of the memory transistor region 1. A floating gate 6 is located extending to the upper of at least part of the selection gate 13. A third gate 14 for controlling the floating gate 6 is formed on the upper of the floating gate 6 via second insulating film 5. The device is formed by a triple layer polysilicon gate process. Such a configuration reduces the width of the floating gate 6 but keeping unchanged the area of the floating gate 6. A separation space 4 between the two transistor regions 1, 2 is reduced and formed by film deposition.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor non-volatile memory devices, particularly electrically rewritable semiconductor non-volatile memory devices that require high integration and high reliability. It concerns sexual memory.

(Prior Art) Generally, as shown in FIGS. 4 and 5, an electrically rewritable semiconductor nonvolatile memory device has a storage transistor region 1 for accumulating charges and a region for performing a selection operation.
In addition, a selection transistor region 2 is provided to prevent a half-select operation in which other non-selected cells are also selected when selecting an arbitrary cell, and the type shown in FIG. 4 has two elements separated to form one cell. Also known is the type shown in FIG. 5, in which a read transistor region 3 is provided in addition to the two elements of the type shown in FIG. 4, and three elements are separated to form one cell. Further, a separation space 4 between the storage transistor region 1 and the selection transistor region 2 and a separation space 5 between the storage transistor region 1 and the readout transistor region 3 are formed by etching using photolithography technology, and the device is Manufactured by a two-layer polysilicon gate process.

(Problems to be Solved by the Invention) As described above, in the conventional electrically rewritable semiconductor nonvolatile memory device shown in FIG. 4, one cell has two transistor regions 1 and 2 for storage and selection. It consists of In this case, the storage and selection transistor regions 1 and 2 are separated by photolithography and etching, but when these processes are used, high integration is limited by the processing accuracy or yield of the device. Further, the memory and selection transistor area 1,
The 20 minute separation amount of 4 is an obstacle to high integration.

Further, in order to facilitate the injection and extraction of electrons into and out of the second gate 6 (here, a floating gate that stores electrons) in the storage transistor region 1, a tunnel is provided for transferring electrons in and out of the storage transistor region 1. It is necessary that the capacitive coupling ratio between the insulating film 7, the first insulating film 8 that provides insulation between gates and substrates, and the drain, channel, and source regions is large.
was formed over a wide area. As shown in FIG. 4, since each transistor region was separated by photolithography, the floating gate 6 was expanded above the channel region in the L direction, which is the direction connecting the drain region and the source region. There was a limit unless the pattern changed. Therefore, when viewed from above the channel region, the floating gate 6 has to be expanded in the W direction, which is rotated by 900 degrees in the L direction, which hinders high integration.

A similar problem also occurs in the conventional electrically rewritable semiconductor nonvolatile memory device consisting of three elements shown in FIG.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor nonvolatile memory device having a storage transistor region and another transistor region in the same cell. An object of the present invention is to provide a semiconductor nonvolatile memory device that enables high integration without reducing the capacitive coupling ratio of an area.

[Structure of the invention]

(Means for Solving the Problems) A typical embodiment of an electrically rewritable semiconductor nonvolatile memory device according to the present invention is shown in FIGS. 1 and 2. As shown in the figure, in the element active region of the device, the second gate 6 of the storage transistor region 1 extends above at least part of the gates of other transistor regions within one cell.

(Function) In the structure configured as described above, a manufacturing method can be used in which the space between each transistor region in one cell is equal to the thickness of the insulating film between the first gate and the second gate, and Since a large second gate area can be secured, the area of one cell can be reduced without reducing the capacitive coupling ratio, and it is possible to miniaturize and highly integrate electrically rewritable semiconductor nonvolatile memory devices.

(Example) The present invention will be described in detail below based on the example shown in the drawings.

FIG. 1 shows an electrically rewritable N-channel type semiconductor nonvolatile memory device showing an embodiment of the present invention. In this figure, one cell in the range Ll consists of two transistor regions 1.25Th for storage and selection. Near the surface of the semiconductor substrate 9 of the first conductivity type (P-type silicon substrate in this embodiment), there is a first conductivity type semiconductor substrate 9 of the second conductivity type through which electrons move. 2nd degree third impurity region io, 11.12 (
In this embodiment, an N-type impurity region) is provided. Among these N-type impurity regions 10, 11, 12, the leftmost N-type impurity region 1o is the drain of the selection transistor region 2. The N-type impurity region 11 in the center is the source of the selection transistor region 20 and the drain of the storage transistor region 1. The N-type impurity region 12 at the right end is the source of the storage transistor region 1. The first high gate 13 (in this embodiment, the selection gate) A of the selection transistor region 2 is formed of a polysilicon film, and is in contact with the lower part of the second gate 6 (in this embodiment, the floating gate) of the storage transistor region 1. A part of the formed 118th edge film 8 becomes the tunnel insulating film 7. The floating gate 6 is connected to the insulating film 8 through the insulating film 8.
It extends to K above at least a portion of the selection gate 13 . Note that this floating gate 6 is formed of a polysilicon film. A third gate 14 (control gate in this embodiment) for controlling the floating gate 6 is formed above the floating gate 6 with a second insulating film 15 interposed therebetween. Note that this control gate 14 is formed of a polysilicon film.

As mentioned above, the embodiment shown in FIG. 1 is fabricated using a three layer polysilicon gate process.

With this configuration, the area of the floating gate 6 can be maintained while reducing the width of the floating gate 6. In addition,
Regarding the direction of the drain and source regions of the storage transistor region 1, the separation space 4 between the two storage and selection transistor regions 1 and 2 is an insulating film portion between the first polysilicon and the second polysilicon, The two transistor regions for storage and selection in the structure of the conventional semiconductor nonvolatile memory device shown in FIG. 4 or FIG.
The separation space 4 between the two is also reduced. That is, this separation space 4 is formed by film deposition without using photolithography technology. By shortening this separation space, the length Ll of one cell can be shortened. Furthermore, if a width similar to that of the floating gate 6 in the conventional structure shown in FIG. 4 is set, the capacitive coupling ratio in the embodiment shown in FIG. The capacitive coupling ratio also has a large value. Conversely, if the capacitive coupling ratio is set to be the same as the capacitive coupling ratio in the structure shown in FIG. 4, the length of one cell in the embodiment shown in FIG. The length of the cell is smaller than the first
The area of one cell in the figure is approximately 80% of the area of one cell in FIG.

That is, in the embodiment shown in FIG. 1, the area of one cell is smaller than the area of one cell in the conventional structure shown in FIG.
In addition, since the capacitive coupling ratio does not change, miniaturization and high integration of semiconductor nonvolatile memory devices can be realized.

FIG. 2 shows another embodiment of the invention.

This embodiment is an electrically rewritable N-channel type semiconductor nonvolatile memory device. In this figure, one cell in the range of "t" is made up of the readout transistor regions 1, 2. 1.Second.
Third. Fourth impurity regions 10, 11, 12, and 16 (N-type impurity regions in this embodiment) are provided. This N
Among the type impurity regions 10.11.12.16, the functions of the two N-type impurity regions 10.11 on the left side are the same as in the previous embodiment, and the N-type impurity region 12 at the center on the right side is the source of the storage transistor region 1. and the drain of the read transistor 3, and the N-type impurity region 16 at the right end is the source of the read transistor 3. The first gate 13 (selection gate in this embodiment) and the fourth gate 17 (readout gate in this embodiment) are formed of a polysilicon film, and are located below the second gate 6 (floating gate in this embodiment). A portion of the first insulating film 8 serves as the tunnel insulating film 7, and the floating gate 6 extends above at least part of the selection gate 6 and the read gate 17 through the first insulating film. It is formed of a polysilicon film as shown in FIG. Further, the third gate 14 (control gate in this embodiment) is formed of a polysilicon film with the second insulating film 15 interposed therebetween. As mentioned above, the embodiment shown in FIG. 2 is fabricated using a three layer polysilicon gate process.

With this configuration, the area of the floating gate 6 can be maintained while reducing the floating gate 6@. In addition, regarding the direction of the drain and source regions of the storage transistor region 1, there is a separation space 4 between the two storage and selection transistor regions 1 and 2, and a separation space 4 between the storage and selection transistor regions 1 and 2.
The isolation spaces 5 between the two transistor regions 1.3 are insulating film portions between the first polysilicon and the second polysilicon, respectively. The separation space 4.5 in the embodiment of FIG. 2 is also smaller than the separation space 4.5 shown in FIG. 4 or 5. That is, this separation space 4.5 is formed by film deposition without using photolithography technology. - By shortening this separation space, it is possible to shorten the length of one cell. Furthermore, when the width of the floating gate 6 in the conventional structure shown in FIG.
The capacitive coupling ratio in the embodiment shown in the figure is larger than the capacitive coupling ratio in the structure shown in FIG. Conversely, if the capacitive coupling ratio in the structure shown in FIG. 5 is set in the example shown in FIG. 2, the length of 1 cell in FIG. The area of 1 cell in Fig. 2 is smaller than 1 in Fig. 5.
This is approximately 80% of the area of the cell.

That is, in the embodiment shown in FIG. 2, the area of one cell is smaller than that of the conventional structure shown in FIG.
In addition, since the capacitive coupling ratio remains unchanged, miniaturization and high integration of semiconductor nonvolatile memory devices can be realized.

In this embodiment, the above effect can also be obtained by extending the floating gate 6 only above the read gate 17.

3(:) to (vl+) show the manufacture of an N-channel type semiconductor nonvolatile memory device (disclosed in FIG. 2) consisting of the three transistor regions 1.2.3 for memory selection and readout shown in FIG. An example of the process is shown.

First, the first conductivity type semiconductor substrate 9 (in this embodiment, a P-type silicon substrate) is separated into an element active region 18 and a field region 19 by a conventional element isolation method (see FIG.
disclosure).

Next, a first insulating film 8 having an appropriate thickness is formed, and then a first polysilicon film 20 is deposited. This first polysilicon film 20 is subjected to heat treatment using impurities to make it conductive.

Furthermore, the area that will become the storage transistor is etched using conventional photolithography technology (see Fig. 3, 11).
disclosure).

Next, an N-type impurity region 11 in the storage transistor region 1 is formed by ion implantation in a self-aligned manner. Furthermore, the second said first insulation H! X8 is formed and the windows in the tunnel area are patterned using conventional photolithography techniques. Subsequently, a tunnel insulating film 7 is formed,
A second polysilicon film 21 is deposited. Then, a heat treatment using impurities is subsequently applied to make the second polysilicon film 21 conductive (FIG. 3 111 disclosed).

Next, slit regions 22 for separating the cells are patterned on the second polysilicon film 21 using a conventional photolithography technique using an anisotropic etching device. Further, a second insulating film 5 is grown, and a third insulating film 5 is grown.
A polysilicon film 2 is deposited, and this third polysilicon film 2
3 is heat-treated with impurities to make it conductive (disclosed in FIG. 3, 1v).

Next, the third polysilicon film 23 and the first . The second insulating film 8.15, the second polysilicon film 21, and the first polysilicon film 20 are patterned at the same time. Further, after removing the resist, the first insulating film 8 is etched. In addition, the above-mentioned first
It is also possible to pattern the first insulating film 8 using an anisotropic ion etching device at the same time as adding the polysilicon film. Furthermore, heat treatment is performed in an oxidizing atmosphere (FIG. 3 V disclosed).

Next, using the gate region of the cell patterned in FIG. 3 as a mask, a low concentration N-type impurity region 24 is formed by ion implantation in a self/line manner to form the drain and source regions of the cell. Furthermore, in order to form a contact region, a high concentration N-type impurity region 25 is formed by ion implantation using conventional photolithography technology (as shown in FIG. 3, 1v).

A protective film 26 is then deposited, contact areas are opened using conventional photolithography techniques, and metal interconnects 27, such as aluminum, are deposited (FIG. 3V, disclosed).

Note that, as shown in FIGS. 1 and 2, the ends of the floating gate 6 in the direction of the drain and source regions of the storage transistor region are connected to all other gates in the same cell.
3.14.17 end portion and the first and second insulating films 8, 15
, and therefore, in the manufacturing process, the third polysilicon film 23 is separated from the first, second insulating films 8, 15 . The second polysilicon film 21. The first polysilicon film 20 can be patterned at one time9, which facilitates manufacturing.

〔Effect of the invention〕

As described above, the present invention has a structure in which the second gate of a storage transistor region having a tunnel insulating film in an element active region of an electrically rewritable semiconductor nonvolatile memory device is located above other transistor regions in the same cell. Furthermore, the third gate of the storage transistor region extends above the second gate, so that the separation portion between each transistor region within one cell is the same as that between the first gate and the second gate. Although it corresponds to the insulating film part, the area of one cell is smaller than the area of one cell of the conventional structure while the capacitive coupling ratio is kept constant. It became possible to promote

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the structure of an N-channel type semiconductor nonvolatile memory device showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view of the structure of an N-channel type semiconductor nonvolatile memory device showing another embodiment of the present invention. 3 is a sectional view showing the manufacturing process of the structure of the N-channel type semiconductor nonvolatile memory device shown in FIG. 2;
FIGS. 4 and 5 are cross-sectional views of the structure of an N-channel type semiconductor nonvolatile memory device showing an example of the conventional art. 6... Second gate, 8... First insulating film. 9... Semiconductor substrate, 10... First impurity region. 11... Second impurity region, 12... Third impurity region. 13...first gate, 14...third gate. 15... Second insulating film, 16... Fourth impurity region. 17...4th gate. Agent Patent Attorney Nori Ken Yudo Takehana Kikuo Figure 1 ('+1i) (v'+'+) Figure 3 ■ Figure 5

Claims (2)

[Claims] (1) A semiconductor nonvolatile memory device characterized by having the following structural requirements: (a) a semiconductor substrate of a first conductivity type; (b) a first semiconductor substrate of a second conductivity type provided near the surface of the semiconductor substrate; second and third impurity regions; c. a first insulating film formed on the semiconductor substrate and having a thin region; d. a first insulating film formed on the semiconductor substrate and connecting the first impurity region and the second insulating film; a first gate located between the impurity region; e, formed on the first insulating film and at least the second gate;
a second gate located between the impurity region and the third impurity region and extending above the first gate; f. a second insulating film formed on the second gate; g;
a third gate formed on the second insulating film; (2) A semiconductor nonvolatile memory device characterized by having the following structural requirements: a, a semiconductor substrate of a first conductivity type; b, a first conductivity type of a second conductivity provided near the surface of the semiconductor substrate; second, third, and fourth impurity regions; c. a first insulating film formed on the semiconductor substrate and having a thin region; d. a first insulating film formed on the semiconductor substrate and having a thin region; a fourth gate located between the second impurity region; e; a fourth gate formed on the semiconductor substrate and located between the third impurity region and the fourth impurity region; , formed in the shape of the first insulating film, and at least the second insulating film.
a second gate located between the impurity region and the third impurity region and extending above the first gate and the fourth gate; g. a second insulating film formed on the second gate; and h, a third gate (3) formed on the second insulating film and located on the first insulating film and located between at least the second impurity region and the third impurity region, and an end of the second gate extending above the first, third, or fourth gate is vertically connected to the first or second insulating film with an end of the first, third, or fourth gate. 3. The semiconductor nonvolatile memory device according to claim 1 or 2, wherein the semiconductor nonvolatile memory device is identical to the semiconductor nonvolatile memory device according to claim 1 or 2.