JPS59154067A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacitance between the first and second gate electrodes and thus contrive to reduce write voltage by a method wherein the second gate electrode is provided on a region including the first gate electrode via the second insulation film so as to bite under the first gate electrode on an element isolation region at least at a part of the second electrode. CONSTITUTION:A PROM memory has a structure having the first gate electrode 20 which crosses a part on the element region 13 via the first gate oxide film 19, both whose end parts extend on a field oxide film, and wherein overhangs 17a and 17b are formed at said parts, and the second gate electrode 22 of the form that a part bites into the overhangs 17a and 17b of said electrode 20 on the region including this gate electrode 20 via the gate oxide film 21. Thereby, since the surface area of the first gate electrode 20 to the second gate electrode 22 can be increased, the capacitance between the first and second gate electrodes can be increased. Therefore, the write voltage into the second gate electrode 22 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[Technical background of the invention]

Nonvolatile semiconductor memory devices, such as FROM (Progr.
amable Read Only Memory)
Conventionally, memory cells having the structure shown in FIGS. 1 and 2 are known. That is, numeral 1 in the figure is a P-type semiconductor substrate, and this substrate 1 is provided with a field oxide film (element isolation region) 3 for isolating element regions 2 . This device region 2 is provided with meter-shaped source and drain regions 4 and 5 that are electrically isolated from each other. A first dirt electrode (floating gate electrode) 7 made of, for example, impurity-doped polycrystalline silicon is formed on a portion of the device region 2 including the channel region between these source and drain regions 4 and 5 via a first dirt insulating film 6. is provided. Further, a second dirt electrode (control gate electrode) 9 made of, for example, impurity doped polycrystalline silicon is laminated on the first gate electrode 7 with a second dirt insulating film 8 interposed therebetween. Note that both ends of the first gate electrode 7 extend in the channel width direction, and parts of these ends overlap on the field oxide film 3. Further, an insulating film 10 is formed on the exposed side surface of the first dirt electrode 7 and around the second dirt electrode 9. In such a FROM, a high voltage is applied to the second dirt electrode 9 and the drain region 5 to inject and accumulate hot carriers generated in the channel region into the first dirt electrode 7 through the first dirt insulating film 6. By changing the threshold voltage (v; &h), a predetermined memory cell is allowed to retain its memory function.

By the way, in the above-mentioned FROM shown in FIGS. 1 and 2, the electrical circuit at the time of writing is shown schematically as shown in FIG. There is a relationship between the voltages VCGO and VCGO as shown in the following equation.

2C3 Vrc = Vcc + VD - (1)
TcT CT=CI+C2+03...(2)
Here, C1 is the capacitance between the substrate 1 and the 70-chip gate electrode 7, C2 is the capacitance between the floating gate electrode 7 and the control gate electrode 9, and C3 is the capacitance between the floating gate electrode 7 and the control gate electrode 9.
and 70-Teinggut electrode 7, and VD indicates the drain voltage.

Writing into the FROM is determined by the voltage VFG of the floating gate electrode 7'), and it is the voltage VCG of the control dart electrode 9 that actually controls fVFG. That is, the proportionality coefficient between VFG and VCC is C2/CT, and in order to be able to write at a low voltage, it is sufficient to simply increase the capacitance C2 between the floating gate electrode 7 and the control gate electrode 9.

[Problems with background technology]

However, in the prior art, a so-called write voltage, which is applied to the control gate electrode even in a 64 EFROM device, requires a high voltage of 21V. In particular, as devices become smaller in the future, lower write voltages will be required. Therefore, one possible method for increasing the capacitance C2 between the dirt electrodes is to make the second dirt insulating film 8 shown in FIG. That is difficult.

[Purpose of the invention]

The present invention aims to provide a semiconductor memory device and a method for manufacturing the same, which can increase the capacitance between the first and second gate electrodes without causing deterioration of device characteristics, and further reduce the write voltage. be.

[Summary of the invention]

The present invention provides a method for forming a second gate electrode on a region including the first gate electrode via a second dirt oxide film so that at least a part of the second gate electrode digs under the first dirt electrode on the element isolation region. By providing 1. The main idea is to increase the capacitance between the second gate electrodes and reduce the write voltage.

That is, the first invention of the present application is a semiconductor memory device including two or more layers of dirt electrodes in an island-like low region of a semiconductor substrate separated by an element isolation region. The first gate insulating film is provided so as to traverse the first gate insulating film and have an end extending over the element isolation region.
A second dirt electrode is provided on the region including the dirt electrode via a second dirt insulating film so that at least a part of the second dirt electrode bites under the first dirt electrode on the element region. .

As the dirt electrode material, for example, polycrystalline silicon containing impurities, amorphous silicon containing impurities, high melting point metal silicide, etc. can be used.

Further, a second invention of the present application provides a method for manufacturing a semiconductor memory device including two or more layers of dirt electrodes in island-like regions of a semiconductor substrate separated by an element isolation region. a step of forming a film/main turn made of a sublimable material in the element isolation region; and a first gate that is covered with the island-shaped region via a first insulating film and whose end portion overlaps the film pattern. A step of forming an electrode material pattern to become an electrode, a step of sublimating and removing the film pattern to form an overhang shape at the end of the electrode material pattern, and a step of forming a second insulating film around the electrode material pattern. a step of depositing a second dirt electrode material film and fully wrapping a portion of the second dirt electrode material film around the overhang portion of the electrode material pattern; A second gate electrode is formed by selectively etching and removing the first gate electrode, a second dirt insulating film, and a portion of the second gate electrode that is partially dug under the first/f''' gate electrode on the element isolation region. The method is characterized by comprising a step of forming.

As the sublimable material, for example, MO or W can be used.

Further, in the above method, the step of sublimating the film/mother turn and the step of forming the second insulating film around the electrode material pattern may be performed simultaneously by heat treatment in an oxidizing atmosphere.

[Embodiments of the invention]

Next, a detailed description will be given of a method of manufacturing a FROM memory cell which is an embodiment of the present invention.

(1) First, after forming a field oxide film (element isolation region) 12 on a P-type silicon substrate 11 by selective oxidation, for example, an island-shaped region (element region) 13 of the substrate 11 separated by the field oxide film 12 is formed. A first thermal oxide film 14 having a thickness of 500× and serving as a first dirt oxide film was formed on the surface by thermal oxidation. Next, a sublimable material film with a thickness of 3000X was applied to the entire surface.
For example, after depositing a Mo film, it was turned and a Mo pattern 15 was formed on the field oxide film 12 (as shown in FIG. 4(a)).

(11) Next, after forming a phosphorescent polycrystalline silicon film with a thickness of, for example, 4000× on the entire surface, this is p-shaped or turned using a photoetching technique to form a layer on the first thermal oxide film 14 and the field oxide film 12. Mo pattern 15
A polycrystalline silicon pattern 16 having a predetermined length in the channel width direction was formed (
(Illustrated in FIG. 4(b)).

G11) Next, thermal oxidation treatment was performed in an oxygen atmosphere at 900°C. At this time, as shown in FIG. 4(C) (M.

The pattern 15 was oxidized and sublimated as molybdenum oxide, and overhang portions 17a and 17b were formed at both ends of the polycrystalline silicon β turn 16 overlapping with the Mo)R turn 15. Subsequently, a second thermal oxidation film 18 with a thickness of 700X was formed around the polycrystalline silicon pattern 16 on which the O-riha/groove parts 17h and 17b were formed by thermal oxidation treatment (see FIG. 4). d) As shown).

(Sequentially, a phosphorus-doped polycrystalline silicon film having a thickness of, for example, 4,000× was deposited on the entire surface, and the polycrystalline silicon was sufficiently wrapped around the overhanging portions 17a and 17b at both ends of the polycrystalline silicon pattern 16. Subsequently, a resist pattern (not shown) is formed by photolithography on the second dirt electrode formation portion of this polycrystalline silicon film, and then a phosphorus-doped polycrystalline silicon film and a second thermal oxide film are formed using the resist pattern or turn as a mask. , the polycrystalline silicon A-turn and the first thermal oxide film were selectively removed by, for example, reactive ion etching (RIE).Thereby, from the substrate 11 side, the first dirt oxide film 19 and the opaque rings were formed at both ends. A first dirt electrode (floating gate electrode) 201 having portions 17g and 17b is laminated on the dirt electrode 20 with a second dirt oxide film 21 interposed therebetween, and both bases are stacked in the channel width direction on the field oxide film 12. An extended second dirt electrode (control gate electrode) 22 was formed. Note that a part of the second dirt electrode 22 overlaps the overhang portion 17 a of the first dirt electrode 20.
r 17 b through the second dirt oxide film 21 . Continuing, Resos) pJ? After removing the turns, using the second dirt electrode 22 as a mask, an n-type impurity,
For example, do you implant arsenic into the substrate 11, activate it, and diffuse it? Type source and drain regions 23. ．． 24 was formed to manufacture a FROM memory cell (as shown in FIGS. 4(e) and 5). Note that FIG. 5 is a plan view of FIG. 4(e).

Therefore, the memory cell of the FROM of the present invention is shown in FIG.
) and, as shown in FIG. 5, cross a part of the element region 13 via the first dirt oxide film 19, and have both ends extending over the field oxide film 12, and have overhangs 17h and 17b at both ends. A second dirt oxide film 21 is formed on the formed first dirt electrode 21 and a region including this dirt electrode 20.
A second dart electrode 2 is shaped so that a part of it bites into the bar hang portions 17m and 17b of the first dart electrode 21 through the
It has a structure with 2. Therefore, the surface area of the first dirt electrode 20 relative to the second dirt electrode 22 can be increased, so that the surface area of the first dirt electrode 20 relative to the second dirt electrode 22 can be increased. The capacitance between the second dart electrodes 20 and 22 can be increased. In fact, if the capacitance in this embodiment is 02' and the capacitance between the first and second gate electrodes in the conventional structure is 02, it becomes C2'#2C2, and the capacitance can be externally increased compared to the conventional structure. . Therefore, the write voltage to the second dirt electrode 22 can be reduced, and the voltage can be lowered in response to miniaturization of memory cells. Moreover, when the capacitance is the same as that of the conventional structure, the area of the floating gate electrode 20 can be reduced, and the element (memory cell) can be miniaturized.

Further, according to the present invention, the first. Second dart electrode 20.22
There is no need to thin the second dirt oxide film 21 between the electrodes 20 and 22 in order to increase the capacitance between them.
A drop in breakdown voltage can be avoided.

Further, according to the present invention, it can be completely removed in an oxidizing atmosphere of 700° C. or higher in the sublimation process of the Mo 2 /4' turn 15, so it can be fully applied to future low-temperature processes.

In the above embodiment, a thermal oxide film formed by thermal oxidation of the second dirt electrode made of phosphorus-doped polycrystalline silicon was used as the material for the second dirt insulating film, but CVD-8
An i02 film may also be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, the first. It is possible to provide a semiconductor memory device in which the capacitance between the second gate electrodes can be increased and the write voltage can be reduced, as well as a method for easily manufacturing such a semiconductor memory device.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional FROM memory cell, Fig. 2 is a cross-sectional view of the two-layer dirt electrode section of the memory cell of Fig. 1 cut in the channel length direction, and Fig. 3 is a cross-sectional view of a FROM memory cell. Schematic diagrams schematically showing electrical circuits during writing, FIGS.
FIG. 5 is a cross-sectional view showing the manufacturing process of a ROM memory cell, and FIG. 5 is a plan view of FIG. 4(e). DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Field oxide film (element isolation region), 13... Element region, 15...
・Mo 4 turns, 16...Li crystal silicon i9 turns, 17 a, 17 b-overhang part, 19
...first gate oxide film, 2Q...first gate electrode (floating gate electrode), 21...second dirt oxide film, 22...second gate electrode (control gate electrode), 23... Meter source area, 24... n+
Type drain region.

Claims (4)

[Claims] (1) In a semiconductor memory device having two or more layers of dirt electrodes in an island region of a semiconductor substrate separated by an element isolation region, a first gate electrode is formed by forming a part of the island region with a first gate insulating film. A second gate electrode is provided on a region including the first dirt electrode, and at least a part of the second gate electrode is provided so that the end portion thereof extends over the element isolation region. 1. A semiconductor memory device characterized in that a second dirt insulating film is provided so as to be inserted under one dirt electrode. (2) Two or more layers of cells are formed in the island-like region of the semiconductor substrate separated by the element isolation region. In manufacturing a semiconductor memory device with a toe electrode, a step of forming a film pattern made of a sublimable material on an element isolation region located at least near an island-like region of a seven-semi-diamond substrate; What kind of electrode material is used to form the first dirt electrode that is covered with the first insulating film and has at least one end slightly overlapping the coating pattern? a step of forming a turn, a step of sublimating and removing the film pattern to form an end portion of the electrode material pattern into an overhang shape, and a step of forming a second insulating film around the electrode material pattern. , a step of depositing a second dirt electrode material film and sufficiently wrapping a portion of the second dirt electrode material film around the overhang portion of the electrode material pattern; and sequentially selectively etching away at least from the second dirt electrode material film to the electrode material pattern. First
A semiconductor memory comprising a step of forming a gate electrode, a second gate insulating film, and a second gate electrode having a shape that is partially dug under the first dirt electrode on the element isolation region. Method of manufacturing the device. (3) The method for manufacturing a semiconductor memory device according to claim 2, wherein the sublimable material is Mo or W. (4) The step of sublimating the film pattern and the step of forming the second insulating film around the electrode material/gut are performed simultaneously by heat treatment in an oxidizing atmosphere. A method for manufacturing a semiconductor storage device.