JPS6370560A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To improve the degree of integration and prevent the generation of a soft error due to radioactive particles such as alpha particles by capacitance formed together with a conductor into a trench shaped to the surface of a semiconductor substrate and a thin-film transistor, which connects a substrate region to the semiconductor substrate and one conductive electrode of which is connected to the conductor. CONSTITUTION:A semiconductor memory cell is constituted of a P-type silicon crystal substrate 101, an N-type buried region 102, a trench forming section 103, an N-type region 104, an insulator film 105, a dielectric 106, a conductor 107, a gate oxide film 108, silicon films 109, 110, a conductor 111, a contact hole 112, P-type silicon 113, a P-type region 114, insulator films 115-117 for dielectric isolation, and the boundary 118 of an active region and an element isolation region. 102, 104, 105 and 106 organize cell capacitance, and 110, 107, 108 and 109 construct an N-type channel thin-film MOSFET. The N-type regions 109 are used as conductive electrodes, and one is connected to the conductor 111 employed as a bit line and the other to the conductor 106 used as a memory node respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Applicability) The present invention relates to a semiconductor memory cell that is suitable for high integration and is less prone to soft errors caused by radioactive particles such as α particles.

(Prior art) A memory cell (hereinafter abbreviated as an ITIC cell) consisting of one transistor and one capacitor as a memory cell for highly integrated semiconductor memory has a small number of constituent elements and can easily miniaturize the memory cell area. Widely used.

Since the output voltage from an ITIC cell is proportional to the capacitance of the memory cell (hereinafter referred to as cell capacitance), the cell capacitance must be made sufficiently large to ensure stable operation even with high integration. In order to achieve even higher integration,
It is necessary to reduce the area of the memory cell itself. Therefore, in order to highly integrate ITIC cells, a cell capacitor with a small area and a sufficient capacitance value is required. Conventionally, as such a cell capacitor, a capacitor formed in a groove portion or a capacitor having a laminated structure has been proposed.

As an example of a cell capacitance formed in a groove, for example, the 1985 International Conference on Electronic Devices (1985 International Conference on Electronic Devices)
nalElecton Device Meeting
) 710-page paper in the proceedings “Buried Stor”
Electrode (BSE) Cell fo
r Megabit DRAMs have been proposed.The 20BSE cell has a cell capacitance in which a conductor is embedded in a trench formed on a silicon substrate with an insulator film sandwiched between the trenches. The embedded conductor is used as an electrode that stores charge (it becomes electrically floating when storing information, hereafter referred to as a storage node), and the silicon substrate is used as an opposite electrode (connected to a constant potential power supply, hereinafter referred to as a cell plate). ).The conductor embedded in the trench is connected to one current-carrying electrode of a switching MO8FET formed on the surface of the silicon substrate.The BSE cell has the following advantages: (1) Multiple adjacent (2) Since the storage nodes of the memory cells are easily insulated, the distance between the memory cells can be made sufficiently small. (2) Since the memory nodes are surrounded by an insulator film, radioactive particles such as alpha particles can be easily isolated. Even if a large amount of minority carriers are injected into the silicon substrate by the incident, the probability that they will be collected in the storage node is low.In other words, soft errors due to radioactive particles such as zero particles are unlikely to occur.

(Problem that the invention attempts to solve) However, BES cells have the following problems.

In the BES cell, the conductivity type of the switching MO8FET connected to the conductor, which is the storage node, and the silicon substrate, which is the cell plate, are different. Therefore, the cell capacitance constitutes a MOS diode with the conductor as the gate electrode and the silicon substrate as the substrate, and the voltage applied thereto is in the direction of depletion or inversion of the silicon substrate surface. Therefore, in order to keep the cell capacitance at a sufficiently large value, it is necessary to make the concentration of the silicon substrate sufficiently high and to reduce the spread of the surface depletion layer of the MOS diode. However, increasing the impurity concentration of a silicon substrate limits the degree of freedom of various devices formed on the silicon substrate. For example, it is difficult to form a CMOS device that requires forming a low impurity concentration well of an opposite conductivity type on the surface of a silicon substrate. Furthermore, the fact that the silicon substrate surface is depleted or inverted means that minority carriers in the silicon substrate are likely to be trapped on this surface. Minority carriers collected on the silicon substrate surface flow into the storage node along this surface. Therefore, there is a limit to the characteristic of BSE cells that "soft errors due to radioactive particles such as alpha particles are unlikely to occur."

One way to solve the problem that BSE cells have is that the conductivity types of the switching MO8FET connected to the conductor, which is the storage node, and the silicon substrate, which is the cell plate, are different. Alternatively, there is a method in which a MOSFET is formed in a well of a conductivity type opposite to that of the silicon substrate. However, in this case, it becomes difficult to connect the substrate of the MO8FET for switching to a constant potential power source. When using a MOSFET on a silicon film, the power supply wiring to the silicon film is connected to the MOSFET in a well of the opposite conductivity type.
In one case where T is used, power supply wiring to the well is required. However, such wiring increases the area of the memory cell and is not suitable for high integration. As a result, in these cases, an unstable MOSFET whose substrate is electrically floating must be used as a switching transistor.

An object of the present invention is to provide a semiconductor memory cell that is suitable for high integration, is less susceptible to soft errors caused by radioactive particles such as alpha particles, and is not limited by the need to increase the impurity concentration of the substrate. .

(Means for Solving the Problems) According to the present invention, there is provided a first conductivity type semiconductor substrate, a second conductivity type buried region formed inside the semiconductor substrate and supplied with a base potential, and a second conductivity type buried region that reaches the buried region. A capacitance and a substrate region constituted by a groove formed on the surface of the semiconductor substrate, an insulating film formed on the surface of the groove, and a conductor formed on the insulating film are connected to the first conductivity type semiconductor substrate. A semiconductor memory cell is obtained, characterized in that it is constituted by a thin film transistor connected to the conductor, and one current-carrying electrode is connected to the conductor.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view showing the structure of another embodiment of the semiconductor memory cell of the present invention, respectively, and FIG. 1(b) is an A-- It is a cross-sectional view when cut at A'. In this figure, 101 is a P-type silicon crystal substrate, 102 is an N-type buried region, 103 is a groove forming part, 104 is an N-type region, 105 is an insulator film, 106 is a conductor, 107.107' is a conductor, 108 1 is a gate oxide film, 109 and 110 are silicon films, and 109 is an N-type region thereof, which becomes the source and drain of the MOSFET. Reference numeral 110 denotes the P wall region thereof, which becomes the chatil region of the MOSFET. 11
1 is a conductor, 112 is a contact hole, 113 is P-type silicon, 114 is a P wall region, 115, 116, and 117 are insulating films for isolation, and 118 is a boundary between an active region and an element isolation region. Note that, in the plan view of FIG. 1(a), some lines are omitted to avoid obscurity.

102, 104, 105, and 106 in this figure constitute the cell volume 1.

N-type regions 102 and 104 are used as cell plates,
A constant potential is supplied through 102. The conductor 106 is used as a J memory node. 110, 107, 108
, 109 constitute an N-type channel thin film MO8FET.

Conductor 107 is used as the gate electrode and word line of this MOSFET. N-type region 109 is used as a current-carrying electrode, and one conductor 111 is used as a bit line.
and the other is a conductor 106 used as a storage node,
each connected. A conductor 107' indicates a word line of an adjacent memory cell when the present memory cells are arranged in a folded bit line configuration.

In the memory cell shown in FIG. 1, the conductivity types of the MOSFETs connected to the cell plate and the storage node are both N-type. Therefore, the voltage applied to the MOS diode that constitutes the cell capacitance is always in the direction that integrates the silicon substrate surface. Therefore, the cell capacitance value is
It has almost no relation to the impurity concentration of 04, and is a large value. Furthermore, since the N-type regions 102 and 104 are connected to a constant potential power supply, minority carriers flowing into these regions quickly flow away to the power supply, and the charges stored in the cell capacitance are less likely to be destroyed.

Furthermore, in the embodiment shown in FIG. 1, the thin film MO8 on the silicon film is
A FET is used as a switching transistor, and the substrate 110 and silicon substrate 101 of this MOSFET are
are the same conductivity type (this means that the switching MO
8FET and the cell plate have the same conductivity type), and the MOSFET substrate 110 is replaced by a silicon substrate 1.
By connecting to 01, it is possible to easily connect the MOSFET substrate to a constant potential power supply.

As described above, in the semiconductor memory cell of the present invention, since the cell capacitance value is formed in the trench, a sufficient capacitance value can be obtained in a small area and is suitable for high integration. Furthermore, soft errors caused by radioactive particles such as alpha particles are less likely to occur.
Unlike BSE cells, there is no restriction that the impurity concentration of the substrate must be high.

For convenience of explanation, the embodiment having the structure shown in FIG. 1 has been used above, but the present invention is not limited to this. The type and conductivity type of the transistor may be other suitable ones.

(Effects of the Invention) As explained above, the memory cell of the present invention is suitable for high integration, is resistant to soft errors caused by radioactive particles such as 0,000 particles, and requires a high impurity concentration in the substrate. It has the effect that there are no such restrictions.

[Brief explanation of the drawing]

Claims (1)

[Claims] a first conductivity type semiconductor substrate; a second conductivity type buried region formed inside the semiconductor substrate and supplied with a reference potential; a groove formed on the surface of the semiconductor substrate so as to reach the buried region; and a groove formed on the surface of the groove. a capacitor constituted by a conductor formed on the insulator film and a substrate region connected to the first conductivity type semiconductor substrate, and one current-carrying electrode connected to the conductor; A semiconductor memory cell characterized by comprising: