JPS6047458A - Soi type mos dynamic memory - Google Patents

Soi type mos dynamic memory

Info

Publication number
JPS6047458A
JPS6047458A JP58154807A JP15480783A JPS6047458A JP S6047458 A JPS6047458 A JP S6047458A JP 58154807 A JP58154807 A JP 58154807A JP 15480783 A JP15480783 A JP 15480783A JP S6047458 A JPS6047458 A JP S6047458A
Authority
JP
Japan
Prior art keywords
si
layer
type
film
poly si
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58154807A
Inventor
Takashi Azuma
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58154807A priority Critical patent/JPS6047458A/en
Publication of JPS6047458A publication Critical patent/JPS6047458A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10829Dynamic random access memory structures with one-transistor one-capacitor memory cells the capacitor being in a substrate trench

Abstract

PURPOSE:To obtain a memory storage having the high degree of integration by superposing an insulating layer and a P type Si layer on a P type Si substrate, forming N type source and drain to the P layer, connecting the source and drain by an N layer in a groove bottom reaching to the substrate and an N type poly Si film being in contact with a groove wall, using a connecting section as an electrode of capacitance and forming an opposite electrode made of poly Si through the insulating film. CONSTITUTION:A thick SiO2 film 22 and P type poly Si 23 in predetermined thickness are superposed on a P type Si substrate 21, and grooves 22a reaching to the substrate 21 are formed through reactive ion etching. A poly Si island A is shaped selectively, and changed into a single crystal Si layer 25 through a laser annealing. A gate oxide film 26 and N type poly Si gate electrodes 27 are formed selectively, the oxide film 26 is removed selectively and P is diffused, and N<-> layers 28 are formed to groove bottoms and the Si layer 25. The whole surface is oxidized, the SiO2 film is left to the wirings 27 and sections in the vicinity of the wirings 27 through selective etching, and the whole is coated with N type poly Si 29 and the poly Si 29 is left on the groove walls through reactive ion etching. SiO2 is removed, an oxide film is shaped, a nitride film is superposed and an insulating film 30 is formed, a poly Si wiring 31 is superposed, and an N<+> layer 4a, a PSG film and an Al wiring to the N<+> layer 4a are formed.
JP58154807A 1983-08-26 1983-08-26 Soi type mos dynamic memory Pending JPS6047458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58154807A JPS6047458A (en) 1983-08-26 1983-08-26 Soi type mos dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58154807A JPS6047458A (en) 1983-08-26 1983-08-26 Soi type mos dynamic memory

Publications (1)

Publication Number Publication Date
JPS6047458A true JPS6047458A (en) 1985-03-14

Family

ID=15592312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58154807A Pending JPS6047458A (en) 1983-08-26 1983-08-26 Soi type mos dynamic memory

Country Status (1)

Country Link
JP (1) JPS6047458A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370560A (en) * 1986-09-12 1988-03-30 Nec Corp Semiconductor memory cell
JPS63158869A (en) * 1986-12-23 1988-07-01 Oki Electric Ind Co Ltd Semiconductor memory
US4918502A (en) * 1986-11-28 1990-04-17 Hitachi, Ltd. Semiconductor memory having trench capacitor formed with sheath electrode
US7534685B2 (en) 2004-03-02 2009-05-19 Infineon Technologies Ag Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor
US7629676B2 (en) 2006-09-07 2009-12-08 Infineon Technologies Ag Semiconductor component having a semiconductor die and a leadframe

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370560A (en) * 1986-09-12 1988-03-30 Nec Corp Semiconductor memory cell
US4918502A (en) * 1986-11-28 1990-04-17 Hitachi, Ltd. Semiconductor memory having trench capacitor formed with sheath electrode
JPS63158869A (en) * 1986-12-23 1988-07-01 Oki Electric Ind Co Ltd Semiconductor memory
US7534685B2 (en) 2004-03-02 2009-05-19 Infineon Technologies Ag Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor
US7629676B2 (en) 2006-09-07 2009-12-08 Infineon Technologies Ag Semiconductor component having a semiconductor die and a leadframe

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