JPS6047458A - Soi type mos dynamic memory - Google Patents

Abstract

PURPOSE:To obtain a memory storage having the high degree of integration by superposing an insulating layer and a P type Si layer on a P type Si substrate, forming N type source and drain to the P layer, connecting the source and drain by an N layer in a groove bottom reaching to the substrate and an N type poly Si film being in contact with a groove wall, using a connecting section as an electrode of capacitance and forming an opposite electrode made of poly Si through the insulating film. CONSTITUTION:A thick SiO2 film 22 and P type poly Si 23 in predetermined thickness are superposed on a P type Si substrate 21, and grooves 22a reaching to the substrate 21 are formed through reactive ion etching. A poly Si island A is shaped selectively, and changed into a single crystal Si layer 25 through a laser annealing. A gate oxide film 26 and N type poly Si gate electrodes 27 are formed selectively, the oxide film 26 is removed selectively and P is diffused, and N<-> layers 28 are formed to groove bottoms and the Si layer 25. The whole surface is oxidized, the SiO2 film is left to the wirings 27 and sections in the vicinity of the wirings 27 through selective etching, and the whole is coated with N type poly Si 29 and the poly Si 29 is left on the groove walls through reactive ion etching. SiO2 is removed, an oxide film is shaped, a nitride film is superposed and an insulating film 30 is formed, a poly Si wiring 31 is superposed, and an N<+> layer 4a, a PSG film and an Al wiring to the N<+> layer 4a are formed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to Sol Ueno 1 having an insulating layer of 13iQ, etc.
The present invention relates to an SOI type MOS dynamic memory using.

[Background of the invention]

In semiconductor LSIs, especially VLSI memory, the element area per memory is becoming smaller and smaller, but as a result, the rate of damage to the memory due to radiation from the outside air, especially alpha rays, is increasing, and reliability is being affected. It is moving in an increasingly unfavorable direction. Therefore, as a way to compensate for these disadvantages, there is a method in which the memory element is formed on a thin silicon layer on an insulating layer.
Or (S-Iconon In5ulator) technology or technology using SOI wafers is becoming popular. This takes advantage of the advantage that even if alpha rays enter the memory element, they enter the insulating layer, so unlike when they enter silicon, minority carriers are not generated and therefore the memory will not be destroyed. It is. As an insulating layer,
Sapphire, SIO, etc. are used, but it is thought that SIO and membranes will become common due to economic efficiency.

On the other hand, in a conventional VL8I dynamic RAM formed on bulk silicon, a structure has been proposed in which a round silicon region dug into a trench or group shape is used as a memory region. That is, this silicon region may be, for example, P-type bulk silicon or N
A thin 8i layer is formed on the surface (side surface of the groove).
A capacitor is formed by covering the capacitor with a 02 film and further covering the top with a polysilicon electrode. A memory structure having trench-shaped memory areas arranged three-dimensionally in this manner is extremely useful for increasing the degree of integration. However, if a trench is dug using an SOI wafer, the surrounding area will be 5i0
Since it is an insulator of the order of 2, it cannot be used as it is to form a memory capacitor, and there has never been an example of a structure having such a groove-shaped memory area used for an SOI type memory.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to form an SOI type MOS dynamic memory with an even higher degree of integration by forming a memory structure having a groove-shaped memory area on the SOI wafer. It is about providing.

[Structure of the invention]

In order to achieve such an objective, the present invention provides a trench in the insulating layer of an 80I wafer that reaches up to the bulk silicon,
A region of conductivity type opposite to that of the bulk silicon is formed at the bottom of the trench, and a source region of the MOS transistor 7 is formed in contact with the side surface of the trench to constitute a transfer region formed in the silicon layer on the insulating layer. A polysilicon film is formed to connect the drain region, and this polysilicon film is used as one electrode of a capacitor constituting the memory region.

As mentioned above, when the insulating layer of an SOI wafer is dug into a groove shape, the surrounding area is an insulator, so in order to form a memory area there, it is necessary to cover the sides of the groove with a suitable semiconductor silicon. There is. In the present invention, a polysilicon film formed in contact with the side surfaces of the trench is used for this purpose. It is conceivable to use epitaxial silicon as the semiconductor silicon film that covers the side surfaces of the trench in this way. In Figure 1,
An example of such a configuration is shown below. In the figure, 2 is a 5102 layer formed on the ItiP-type silicon, and 3 is a P-type silicon layer formed on it. Reference numeral 4 designates a P-type silicon layer 3vc, and the nine N regions constitute the source and drain regions of the MOS transistor. 5 designates a gate insulating film, and 6 designates a gate electrode. Groove 2 in the old 02 layer 2 above
A is provided, and its side surface is coated with P by epitaxial selection technology.
After filling with type epitaxial silicon, the side surfaces of the buried P type epitaxial layer 7 are exposed by trench etching and an N- region 8 is formed.
An insulating film 9 and a polysilicon thin film 10, each of which is a stack of a 3iC)2 film and a Si3N4 film, are stacked. This field memory area is formed by a P-type epitaxial layer γ as shown in FIG.
It is composed of an N- region 8 formed inside, an insulating M9 thereon, and a polysilicon thin film 10 thereon, and the N-region 4 is adjacent to the N- region 8 and serves as an input.

However, such a structure using epitaxial silicon is expensive because the epitaxial process itself has low productivity and requires a long reaction time because the groove 2 is deep. The present invention eliminates this disadvantage in terms of cost by using polysilicon instead of epitaxial silicon. In that case, at the end of the memory area, when etching the Sin layer, bulk silicon appears as the end point, so in order to maintain insulation in the lower part of the memory area, impurities of the opposite conductivity type to the bulk silicon are introduced. It is a PN junction.

In the configuration shown in Figures 1 and 2, both ends of the memory area have an NP junction on the input side and an NP junction on the termination side, both of which have extremely high insulation, and are also surrounded by an 8192 layer 2, so the insulation is also high. expensive. On the other hand, in the structure using a polysilicon film as in the present invention, insulation is inevitably obtained on the input side by the source/drain regions of the MOS transistors constituting the transfer region, and the surrounding S
The same applies to the insulation properties of the i20 layer. However, as mentioned above, the termination side is insufficient as it is, so a PN junction is formed. Hereinafter, the present invention will be explained in detail using Examples.

[Embodiments of the invention]

FIG. 3 is a sectional view showing an embodiment of the present invention.

SOI wafer (DS i 02 ) The sides of the grooves 2a formed in the layer 2 to reach the P-type bulk silicon 1 are directly covered with a polysilicon layer 11, and the 9N-type is formed by phosphorus treatment to form a path for signals from the input side. Moreover, on this polysilicon layer 11, thin Si 02 g and 5t3N4
A capacitive wiring is formed by disposing an insulating film 9 in which films are laminated and using a polysilicon thin film 10 as a counter electrode.

Further, 4a is an N region constituting the source/drain region of the MOS transistor, and 4b is also an N- region, but the input side of the memory is in contact with the N- region 4b and is connected to the N-P junction. High insulation is inevitably maintained. On the other hand, the bulk silicon 1 at the bottom of the trench 211 also has N-
A region 12 is formed, and as shown in FIG. 4, both the input side and the termination side are connected by a PN junction to maintain insulation of the memory.

Next, the manufacturing method of the above structure is shown in FIGS.
) and FIG. 6.

First, a relatively thick 5i02 layer (3
μm or more) 22 (Fig. 5(a)).

Next, a polysilicon layer 23 of a predetermined thickness is deposited over the entire surface (FIG. 5(b)).

Next, using a photoresist (not shown) as a mask, the polysilicon layer 23 is first subjected to RIE into a predetermined pattern, and then, using the polysilicon layer 23 as a mask, the entire stow layer 22 is
2E to form a groove 22M.

In RIE, the etching end point is the bulk silicon 21 (FIG. 5(C)).

Next, an island made of a polysilicon layer as shown in area A is formed using a rigid photoresist mask 24 (FIG. 5(d)) shown by broken lines. Next, this island is recrystallized by known laser annealing to form a single crystal silicon layer 25 (FIG. 5(e) %, (f
); FIG. 5(f) is a view taken along the line ff@ of FIG. 5(c). ) By the way, island-heated polysilicon is easily recrystallized. If it is difficult to completely recrystallize a polysilicon layer of the desired thickness by laser annealing, it is necessary to use polysilicon from the beginning. layer 23
After recrystallization, a P-type epitaxial layer 25' is deposited using the epitaxial selective deposition method as shown in FIG. Take measures to compensate for this. At this time,
An epitaxial layer 25' is deposited 75 on the bottom of the layer 22a and the inner region on the single crystal silicon layer 25, so that the sum of the thicknesses of the single crystal silicon layer 25 and the epitaxial layer 25' becomes the single crystal layer in FIG. 5(f). Just like the silicon layer 25, it may have a desired thickness.

Next, a gate oxide film (FIG. 5(i)) is formed to form a MOS transistor constituting a transfer region.

26) in (j) is formed, and a polysilicon layer is similarly deposited for the gate electrode, and after being made pN type by phosphorus treatment, etching is performed using the patterned photoresist as a mask to form a polysilicon wiring 27 ( Figure 5 (g
)). In this case, since the polysilicon layer is also deposited within the trench 22a, R
Both IE and isotropic etching must be used together.

After forming the polysilicon wiring 27 in this way, the gate oxide film other than the gate region is removed and phosphorus is deposited, or ion implantation of phosphorus or arsenic is performed through the gate oxide film 26.
N- regions 28 are formed at the bottom of trench 222 and in the source/drain regions of single crystal silicon layer 25. Further, the entire surface is oxidized to form an 8102 film, and etching is performed using a photoresist mask as shown by the broken line in FIG. leave. Next, a polysilicon layer is deposited to form a capacitor electrode, and after being made N-type by phosphorus treatment, RIE is performed to form an N-type polysilicon layer 29 only on the side surfaces of the trench 22a (see FIG. 5(+)).
, (j) ; In addition, Fig. 5 0) is
(It is a direct appeal figure).

The remaining 5i02 film is removed by etching, gate oxidation is performed to form a capacitor insulating film, and an insulating film 30 is formed by depositing a 3 i3 N4 film in order to increase the capacitance for memory. Next, a polysilicon layer is deposited to form the other capacitor electrode, and after being converted into N-type by phosphorus treatment, etching is performed using a photoresist mask (not shown) to form polysilicon wiring 31 (the first Figure 5 (j)).

Next, using this polysilicon wiring 31 as a mask, arsenic or phosphorus is deposited over the N- region shown by C in FIG. 5 (11) between both wirings, thereby forming an N-region corresponding to 48 in FIG. do.

Finally, the entire surface is covered with a PSG film, and this is photo-etched to form a contact hole on the N+ region. After aluminum is further deposited on the entire surface, this is photo-etched to form a contact hole on the N+ region in the contact hole. By forming contacting aluminum wiring, a memory element as shown in FIG. 3 can be formed. However, the configuration corresponding to this last step is omitted in Fig. 3.
Figures (h) to (j) show only a portion in detail, and since the left and right parts are the same, they are omitted as appropriate.

The above explanation can be applied in exactly the same way to a structure in which the conductivity type of each semiconductor layer is completely reversed.

〔Effect of the invention〕

As explained above, according to the present invention, a groove reaching the bulk silicon of the first conductivity type is provided in the insulating layer of the SOI wafer, a region of the second conductivity type is formed at the bottom of the groove, and a groove of the second conductivity type is formed at the bottom of the groove. The source region of the MOS (MOS) run lister formed in the silicon layer on the insulating layer is in contact with the side surface of the region.
By forming a polysilicon film of the second conductivity type connected to the drain region and using it as one electrode of the capacitor,
It is now possible to apply a trench-type memory structure to an SOI wafer), and a highly integrated MOS dynamic memory can be formed. Moreover, as described above, since polysilicon is used as the capacitor electrode, it has the advantage of being cheaper than when epitaxial silicon is used.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing an example in which a trench-shaped memory structure is applied to a SOR wafer, and the memory is realized using epitaxial silicon as a capacitor electrode formed on the side surface of the trench. 3 are cross-sectional views showing one embodiment of the present invention, FIG. 4 is a diagram for explaining its memory structure, and FIGS. 5(,) to (J) and FIG. It is a process diagram for explaining an example. 1 fist・晦・P type bulk silicon, 2・・1l-stoz
Layer, 22a...Self-groove, 3aφ...P-type silicon layer, 4
a...-N region, 4b111.12...N- region, 5...gate insulating film, 6...gate electrode,
9... Capacitor insulating film, 1011... Polysilicon thin film. I-1^ Figure 1 Figure 4 Figure 5 Figure 5 Figure 5

Claims (1)

[Claims] An insulating layer and a silicon layer having a first conductivity type are laminated in this order on a silicon layer having a first conductivity type, and the silicon layer has a second conductivity type opposite to the first conductivity type. A transfer region is provided to serve as the source O drain of the MOS (MOS) run lister, and a trench reaching the bulk silicon is provided in the insulating layer, a region having the second conductivity type is provided at the bottom of this trench, and an upper forming a polysilicon film of a second conductivity type in contact with the (11) surface of the trench to connect a region of the second conductivity type constituting the source/drain and a region of the second conductivity type at the bottom of the trench;
An SOI type MOS characterized in that this polysilicon film is used as one electrode of a capacitor constituting a memory area, and a polysilicon film formed by interposing an insulator on this polysilicon film is used as the other electrode. dynamic memory.